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[VHDL-FPGA-Verilog] Xilinx spartan 6 DDR 测试源代码 DL : 1: Xilinx FPGA Spartan 6 上可运行的软核microblaze以及外设DDR, SPI,UART等测试代码
Update : 2011-09-22 Size : 17.62mb Publisher : jameszhou9019
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] DDR_SDRAM_Controller DL : 0: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Update : 2025-02-17 Size : 662kb Publisher : 钟方
[VHDL-FPGA-Verilog] ddr_cntl_a_withtb DL : 0: arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
Update : 2025-02-17 Size : 2.27mb Publisher : yourname
[VHDL-FPGA-Verilog] DDRSDRAM DL : 0: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
Update : 2025-02-17 Size : 998kb Publisher : 飞翔
[VHDL-FPGA-Verilog] ddr DL : 0: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Update : 2025-02-17 Size : 999kb Publisher : yuling
[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Update : 2025-02-17 Size : 112kb Publisher :
[VHDL-FPGA-Verilog] ddr_ctrl DL : 0: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Update : 2025-02-17 Size : 27kb Publisher : 王郁
[VHDL-FPGA-Verilog] DDRSDRAM DL : 0: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Update : 2025-02-17 Size : 463kb Publisher : 张宁
[VHDL-FPGA-Verilog] rtl DL : 0: DDR控制器已通过FPGA 验证大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Update : 2025-02-17 Size : 51kb Publisher : kin
[VHDL-FPGA-Verilog] DDR_SDRAM DL : 0: 利用fpga读写ddr的源代码实测可以使用-Ddr use FPGA to read and write the source code can use the measured
Update : 2025-02-17 Size : 463kb Publisher : 朱宝军
[VHDL-FPGA-Verilog] DDR_SDRAM DL : 0: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Update : 2025-02-17 Size : 661kb Publisher : 黄达
[Software Engineering] DDR2_hardcore_userguide DL : 0: xillinx Spartan6 FPGA DDR 接口设计指南-xillinx Spartan6 FPGA DDR Interface Design Guidelines
Update : 2025-02-17 Size : 2.22mb Publisher : james
[VHDL-FPGA-Verilog] ddr_sdr_V1_1 DL : 0: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Update : 2025-02-17 Size : 37kb Publisher : jordanliang
[VHDL-FPGA-Verilog] Twister_DDR_SDRAM_Board_Manual DL : 0: Twister DDR EP1C6Q240 FPGA 开发板原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
Update : 2025-02-17 Size : 1.38mb Publisher : SEED
[VHDL-FPGA-Verilog] ddr_code DL : 0: 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware description language
Update : 2025-02-17 Size : 11kb Publisher : 阳阳
[VHDL-FPGA-Verilog] FPGA-DDR-SDRA DL : 0: 基于FPGA 的DDR SDRAM高速数据采集的应用-DDR SDRAM high-speed FPGA-based data acquisition applications
Update : 2025-02-17 Size : 302kb Publisher : 周勇
[VHDL-FPGA-Verilog] ddr DL : 0: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Update : 2025-02-17 Size : 175kb Publisher : 洪依
[VHDL-FPGA-Verilog] FPGA-SDRAM-control-code DL : 0: 该程序是FPGA控制DDR SRAM的控制源代码，使得SDRAM的控制变得简单。-This program is DDR SDRAM control code ,it makes the operation of SDRAM more easy.
Update : 2025-02-17 Size : 41kb Publisher : didi
[VHDL-FPGA-Verilog] DDR-SDRAM_IP_core DL : 0: DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Update : 2025-02-17 Size : 463kb Publisher : zyy

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