Search - fpga elevator

[VHDL-FPGA-Verilog] DEMO22

Description: ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ　环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
Platform: | Size: 598016 | Author: liu | Hits:

Description: Verilog在maxpuls2下开发的电梯控制器的文档（包括代码），其中说明十分详尽-Verilog maxpuls2 under development in the elevator controller files (including code), It showed very detailed
Platform: | Size: 73728 | Author: 余远恒 | Hits:

[File Format] te3560

Description: 基于VHDL语言的实用电梯控制器的设计 -based on VHDL practical elevator controller design based on VHDL practical Elevator Controller VHDL design based on the practical design of the elevator controller based on VHDL practical elevator controller design
Platform: | Size: 94208 | Author: | Hits:

[assembly language] lift

Description: 用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.-Using FPGA to control the lift, the realization of five-story elevator landing and take-off control, the use of VHDL editing process.
Platform: | Size: 275456 | Author: 郭翠双 | Hits:

[VHDL-FPGA-Verilog] dianti

Description: vhdl代码：电梯控制器程序设计与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: Elevator controller design and simulation program! FPGA beginner who can refer to reference! ! Relatively simple
Platform: | Size: 162816 | Author: daxiadian2 | Hits:

[VHDL-FPGA-Verilog] dianti

Description: 以FPGA技术为基础，以VHDL为语言，以QuartusII为工具，设计一个5层楼的电梯控制器-To FPGA technology, to VHDL language to QuartusII as a tool to design a 5-story elevator controller
Platform: | Size: 2048 | Author: linyao | Hits:

[VHDL-FPGA-Verilog] Elevator

Description: 基于FPGA的6层电梯控制器，使用VHDL编程，用quartus ii进行仿真模拟-Elevator Controller
Platform: | Size: 162816 | Author: xieyi | Hits:

[VHDL-FPGA-Verilog] lift.vhd

Description: 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically determine the next line, as well as alarm, forced open the door and other features ~ ~
Platform: | Size: 1024 | Author: 董灏 | Hits:

[DSP program] DSPFPGA

Description: 针对电梯数据采集数目较多和数据处理复杂等特点,提出了基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)的电梯智能数据采集系统。在介绍了系统整体结构及各组成子模块后,给出了模块与器件之间硬件接口设计思路和架构,描述了整个系统的软件框架,设计了DSP、AD采样、网络通信和抗干扰等程序。整个系统在工程应用中易于实现,具有很好的推广价值-n accordance with the characteristic of elevator for the large number of data acquisition and handling data complicated, an el- evator data acquisition system based on digital signal processor (DSP) and field programmable gate array (FPGA) is given. After system structure and modules are introduced, the design of interfaces of the hardware and framework between modules and devices are provided, the software design used in the system is described, the DSP, AD sampling, network communication
Platform: | Size: 179200 | Author: 将建 | Hits:

[VHDL-FPGA-Verilog] FPGA_SOPC

Description: FPGA/SOPC开发快速入门教程，FPGA 在复杂逻辑电路以及数字信号处理领域中扮演者越来越重要的角色，SOC（片上系统）以其低功耗，高性能，低成本，高可靠性等优点成为嵌入式系统的发展趋势。作-QUARTUS II platform based on the VHDL language elevator system control procedures.
Platform: | Size: 1512448 | Author: 蔡秀雄 | Hits:

[VHDL-FPGA-Verilog] dianti

Description: FPGA的电梯控制程序，用vhdl语言实现电梯的控制的代码-FPGA elevator control program, using vhdl language implementation code for the control of the elevator
Platform: | Size: 3072 | Author: 萤火虫 | Hits:

[VHDL-FPGA-Verilog] wodewenjian

Description: 基于FPGA的电梯控制系统的设计将电梯的运行状态划分为开门，一层，二层，三层，四层五个状态，设一层开门为电梯的初始状态，up1,up2,up3分别作为一层，二层，三层的上升请求，四层没有上升请求；down2,down3,down4分别作为二层，三层，四层的下降请求，同理一层是没有下降请求的；s1,s2,s3,s4分别作为一层，二层，三层，四层的停站请求；x1,x2,x3,x4分别作为一层，二层，三层，四层的停站请求显示；door作为门的状态，“0”表示关，“1”表示开；mode作为电梯的运行模式，这里可以用一个seg模块将楼层的显示转换为数码管显示。 -The elevator control system based on FPGA design Will lift operation into a layer, the second door, and three layers, four layers, one of five layers of the elevator opened for the initial state, respectively, up2 up3 up1, as a layer 2 and layer 3, the rise and rise no request for four layers, Down2 down3 down4, respectively, as a second, third, fourth floor request, a drop down the request is not, S1, s2, s3, respectively, as a layer s4 2, 3, 4 stops, Clamps its x1, x2, respectively, as a x4 x3 layer 2 and layer 3, 4, stop that request, As the door, held "0", "1" say, Mode of operation mode, as the elevator here can use a seg module will be converted to digital display floor pipe display.
Platform: | Size: 1024 | Author: 吴海霞 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 在该文档中详细介绍了如何用FPGA语言对电梯进行群控管理。-In the document describes in detail how to use FPGA language elevator group control management.
Platform: | Size: 7342080 | Author: wangbaohua | Hits:

[VHDL-FPGA-Verilog] VHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

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[VHDL-FPGA-Verilog] DEMO22

[VHDL-FPGA-Verilog] dianti

[File Format] te3560

[assembly language] lift

[VHDL-FPGA-Verilog] dianti

[VHDL-FPGA-Verilog] dianti

[VHDL-FPGA-Verilog] Elevator

[VHDL-FPGA-Verilog] lift.vhd

[DSP program] DSPFPGA

[VHDL-FPGA-Verilog] FPGA_SOPC

[VHDL-FPGA-Verilog] dianti

[VHDL-FPGA-Verilog] wodewenjian

[VHDL-FPGA-Verilog] FPGA

[VHDL-FPGA-Verilog] VHDL-dianti

[VHDL-FPGA-Verilog] dianticontrol

[VHDL-FPGA-Verilog] ControllingElevatorbyFPGACode.txt

[VHDL-FPGA-Verilog] FPGA

[VHDL-FPGA-Verilog] diantikongzhixiqi2

[VHDL-FPGA-Verilog] elevator

[VHDL-FPGA-Verilog] elevator

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