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[VHDL-FPGA-Verilogusb_jtag

Description: FPGA、CPLD芯片的usb数据下载线,下载速度是并口的5位,内有原理图用程序-FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in
Platform: | Size: 234496 | Author: 李聚光 | Hits:

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