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[Other] Lattice_ISP_Downloader

Description: FPGA-Lattice ISP 下载线，官方说明，英文。
Platform: | Size: 66167 | Author: 威威 | Hits:

[VHDL-FPGA-Verilog] 并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)

Description: 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
Platform: | Size: 2302730 | Author: mikeldm@163.com | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 677888 | Author: 钟方 | Hits:

[Other] Lattice_ISP_Downloader

Description: FPGA-Lattice ISP 下载线，官方说明，英文。-FPGA-Lattice ISP download cable, the official description, English.
Platform: | Size: 65536 | Author: 威威 | Hits:

[Software Engineering] xp2syscloclkpll

Description: 这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多-Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar
Platform: | Size: 641024 | Author: | Hits:

[Other Embeded program] PLDDOWNL

Description: LATTICE公司的CPLD/FPGA的ISP下载电缆PCB设计图。-LATTICE company s CPLD/FPGA s ISP download cable PCB design.
Platform: | Size: 29696 | Author: 吕常智 | Hits:

[VHDL-FPGA-Verilog] VGA_1024×768×85

Description: 用verilog hdl实现的VGA显示彩条信号，其中包括VGA时序、竖彩条、横彩条、棋盘格-Using verilog hdl realize the VGA display color signals, including VGA timing, vertical color, Wang Cai, the checkerboard lattice
Platform: | Size: 450560 | Author: 华磊 | Hits:

[VHDL-FPGA-Verilog] music

Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。 -Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
Platform: | Size: 8192 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] colorful_signal

Description: 设计并调试好一个VGA彩条信号发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 由系统提供的时钟源引入扫描信号，根据VGA彩色显示器的工作原理，设计出各种颜色编码和行场扫描信号。将并口线从计算机并口与CPLD/FPGA适配板连接好，然后将VGA接口与彩色显示器连接好，彩条信号就可以在显示器中产生，通过按键可以改变产生彩条的方式，共六种彩条信号，两种横彩条，两种竖彩条，两种棋盘格。本实验运用层次化设计出VGA彩条信号发生器，由行场信号模块模块和彩条信号发生模块构成，彩条信号发生器的顶层原理图如图10.7 所示. -err
Platform: | Size: 7168 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] MICO8_DEMO_03_18_08.ZIP

Description: Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。-Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to support the GCC compiler. Lattice can all FPGA and MachXO devices use. In this case contains examples and documentation. On the use of Lattice devices users or learning CPU design personnel have a higher reference value.
Platform: | Size: 3317760 | Author: ymjcloud | Hits:

[SCM] ledhzxs

Description: 以FPGA芯片为核心，扩展必要的外围电路，制作一个16*16LED点阵的汉字显示屏，使之能显示16*16LED点阵的汉字4个，如“一”，“二”，“三”，“四”等。要求显示的汉字无闪烁。每个汉字停留时间1秒。-To FPGA chip as the core, the expansion of the necessary external circuit, producing a lattice of 16* 16LED display of Chinese characters so that it can display 16* 16LED lattice four Chinese characters, such as " 1" , " two" , " three" , " four" and so on. Request to display Chinese characters without blinking. Residence time of each character one second.
Platform: | Size: 263168 | Author: 庄青青 | Hits:

[VHDL-FPGA-Verilog] A01

Description: 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilinx, Lattice, Altera and other manufacturers of the CPLD/FPGA.
Platform: | Size: 3234816 | Author: 李德明 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM

Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
Platform: | Size: 676864 | Author: 黄达 | Hits:

[VHDL-FPGA-Verilog] Lattice-Machxo-FPGA-Loader

Description: Application note (source code + documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.-Application note (source code+ documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.
Platform: | Size: 664576 | Author: M V | Hits:

[VHDL-FPGA-Verilog] VHDL-FPGA-xilinx-altera-frily

Description: VHDL的经典经验。相当的不错，一个多年开发FPGA的工程师自己的记录，适用于ALTERA,XILINX,LATTICE等FPGA的开发。希望对大家有用。-VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera
Platform: | Size: 3913728 | Author: 何思涵 | Hits:

[VHDL-FPGA-Verilog] ISPPCBforFPGA

Description: Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB-Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB
Platform: | Size: 183296 | Author: kenny | Hits:

[Other] LatticeIspLever

Description: Lattice ispLever 培训教程——基于新的莱迪斯FPGA的设计流程 -Lattice ispLever
Platform: | Size: 1506304 | Author: luanting | Hits:

[VHDL-FPGA-Verilog] vga

Description: 用VHDL实现VGA显示,在VGA显示器上显示彩色条，用的FPGA是Lattice公司的XP2-5.程序测试通过，附图片资料-VHDL implementation with VGA display, the VGA color monitor display section, with the FPGA, Lattice' s XP2-5. Procedures tested, with a picture information
Platform: | Size: 716800 | Author: | Hits:

[Other] mentor_all

Description: lattice fpga solution for 7:1 DESERIALIZATION INTERFACE ,LIKE FAST LINK, CAMERA LINK.
Platform: | Size: 277504 | Author: rozenan | Hits:

[Other] FX2LP Crosslink FPGA Source Code

Description: FX2LP Crosslink FPGA Source Code
Platform: | Size: 2883584 | Author: 杜掌柜 | Hits:
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