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[VHDL-FPGA-VerilogVHDL_DMF

Description: Vhdl实现扩频通信匹配滤波器,书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time.
Platform: | Size: 1024 | Author: 刘小姐 | Hits:

[CommunicationAnFPGASoftwareDefinedUltraWidebandTransceiver

Description: Increasing interest in ultra-wideband (UWB) communications has engendered the need for a test bed for UWB systems. An FPGA-based software-defined radio provides both postfabrication definition of the radio and ample parallel processing power. This thesis presents the FPGA design for a software-defined radio targeted to impulse ultra-wideband signals. The system is capable of an effective sampling frequency of up to 8 G-samples/s using timeinterleaved sampling with eight 1-GHz ADCs. The system is also capable of transmitting UWB pulses using a transmitter board controlled by the FPGA. In this thesis, the FPGA design used to capture and export data from the eight ADCs is presented, along with two systems which make use of the transceiver: a pilot-based matched filter communications system, and a remote vital signs monitor.
Platform: | Size: 1396736 | Author: chaiwat | Hits:

[Embeded-SCM Develop18a

Description: 匹配滤波器设计,VERILOG实现的,比较好的哦-Matched filter design, VERILOG implementation, and better oh
Platform: | Size: 51200 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilogdmfilter

Description: gps接收机伪码捕获时采用的匹配滤波器,能完成接收码的捕获。-gps receiver pseudo-code used to capture the matched filter, receiving yards to complete the capture.
Platform: | Size: 1024 | Author: 易凯 | Hits:

[Software EngineeringFPGA-AFC-Phase-tracking

Description: 本论文主要研究并设计实现了扩频通信接收系统的跟踪模块,接收系统主要由数字下变频、数字匹配滤波器、差分解调、自动频率跟踪处理等模块组成。-This paper mostly introduces and implementes the receiving system, the receiver unit mainly consisted of the digital down converter, matched filter, differential demodulator, output processor and AFC module.
Platform: | Size: 402432 | Author: gao xiangfeng | Hits:

[Com Portd974d4330bf7

Description: 这是一个非常完整的qpsk调制解调用fpga实现的工程,在工程中已经能够正常使用,使用的quartus ii 开发,使用Verilog语言,文件中还包含了各种滤波器的系数文件,还有matlab仿真文件,整个工程包含从串并变换,相位映射,到成型滤波,中通滤波,cic滤波,调制,再到解调过成的下变频,匹配滤波,载波提取,位定时,判决,整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implementation of the project, the project has been able to properly use the Quartus II development, the use of Verilog language, the file also contains the files of various filter coefficients, and MATLAB simulation files, including the entire project from the string and transform, phase mapping, molding in filtering, filtering, CIC filtering, modulation, and demodulation frequency, a matched filter, carrier extraction, timing, judgment, the whole course)
Platform: | Size: 13488128 | Author: maerzaizai | Hits:

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