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[Other resource] MyClockTest

Description: 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function.
Platform: | Size: 507269 | Author: blacksun | Hits:

[VHDL-FPGA-Verilog] MyClockTest

Description: 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function.
Platform: | Size: 506880 | Author: blacksun | Hits:

[VHDL-FPGA-Verilog] uart232

Description: 基于FPGA的异步串行通行，用MAX232转化的，利用VHDL语言写的，都已调通，有很大的使用价值！-FPGA-based asynchronous serial passage, with MAX232 conversion using VHDL language written in, have been transferred pass, there is a great value!
Platform: | Size: 1344512 | Author: xuyanhui | Hits:

[VHDL-FPGA-Verilog] UFTtest

Description: 基于fpga的verilog写的MAX2的ufm模块使用实例-Module uses examples based on the fpga' s verilog wrote the MAX2 the ufm
Platform: | Size: 95232 | Author: yeguowu | Hits:

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