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[Other resource] mlite.tar

Description: Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
Platform: | Size: 100364 | Author: xinyang | Hits:

[Other resource] MIT_MIPS_Core.tar

Description: 麻省理工的一个实验室实现的MIPS IP CORE，可以在FPGA上跑通 -a Massachusetts Institute of Technology laboratory achieved MIPS IP CORE, the FPGA can run on Link
Platform: | Size: 28647 | Author: xinyang | Hits:

[Other resource] CTDSP

Description: 本源码经过上机调试,是CT算法在TI的CCS下编程 可以在DSP硬件和软件仿真条件下运行,同时对CT算法在ARM,MIPS,PC,FPGA等上实现都有借鉴意义.搞CT等重建算法的人值得一看
Platform: | Size: 16502 | Author: 9311066 | Hits:

[VHDL-FPGA-Verilog] mlite.tar

Description: Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
Platform: | Size: 100352 | Author: xinyang | Hits:

[VHDL-FPGA-Verilog] MIT_MIPS_Core.tar

Description: 麻省理工的一个实验室实现的MIPS IP CORE，可以在FPGA上跑通 -a Massachusetts Institute of Technology laboratory achieved MIPS IP CORE, the FPGA can run on Link
Platform: | Size: 28672 | Author: xinyang | Hits:

[DSP program] CTDSP

Description: 本源码经过上机调试,是CT算法在TI的CCS下编程 可以在DSP硬件和软件仿真条件下运行,同时对CT算法在ARM,MIPS,PC,FPGA等上实现都有借鉴意义.搞CT等重建算法的人值得一看-Following on the source machine debugging is CT algorithm in TI under the CCS program in DSP hardware and software running under simulation conditions, while CT algorithm in ARM, MIPS, PC, FPGA, etc. have referential significance achieve. Engage in CT reconstruction algorithm, such as a person worth a visit
Platform: | Size: 328704 | Author: 9311066 | Hits:

[Other] 16wsclq

Description: 16位微处理器在FPGA上的设计与原理实现 FPGA硬件仿真平台和MIPS芯片组的设计与实现-16-bit microprocessor in the FPGA on the FPGA design and the principle of the realization of MIPS hardware simulation platform and chipset design and implementation of
Platform: | Size: 1994752 | Author: 黄诗杰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] FPGA_design_of_a_pipelined_CPU

Description: 基于FPGA流水线CPU控制器的设计与实现：在FPGA上设计并实现了一种具有MIPS风格的CPU硬布线控制器。-FPGA design of a pipelined CPU：a hard-wiring CPU controller with a MIPS-style is designed in FPGA.
Platform: | Size: 274432 | Author: 卢刚 | Hits:

[VHDL-FPGA-Verilog] CU

Description: mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
Platform: | Size: 6144 | Author: dukenunee | Hits:

[VHDL-FPGA-Verilog] fpGAbased-system-design

Description: 基于FPGA系统设计 本案例利用ALTIUM设计一个数字可控的混响系统，在这个系统中将把MIPS处理器、 IIS 控制器、SPI控制器、SRAM控制嵌入到FPGA内部实现图1的功能结构。 -FPGA-based system design This case the use of the ALTIUM design a digital controlled reverberation system, MIPS processors will be in this system, the IIS Controller, SPI controller, SRAM control embedded within the FPGA to achieve the functional structure of Figure 1.
Platform: | Size: 854016 | Author: vipjvs | Hits:

[VHDL-FPGA-Verilog] MIPS-processor-Verilog-code

Description: 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)
Platform: | Size: 7168 | Author: ZLS | Hits:

[LabView] 0134565673RobustC

Description: Embeded-SCM Develop ARM-PowerPC-ColdFire-MIPS Embeded Linux SCM VxWorks uCOS DSP program Windows CE VHDL-FPGA-Verilog Other Embeded program
Platform: | Size: 4175872 | Author: otman | Hits:

[VHDL-FPGA-Verilog] s_mips

Description: FPGA verilog mips processor - pipeline reference
Platform: | Size: 2048 | Author: howyaaa | Hits:

[VHDL-FPGA-Verilog] VHDLshipincaijixitong

Description: 利用ALTIUM DESIGNER设计一个CMOS摄像头采集系统，在这个系统中将把MIPS处理器、IIC控制器、AD视频接口、LCD控制器、SRAM控制嵌入到FPGA内部实现图 1的功能结构。-Use of the ALTIUM DESIGNER designed a CMOS camera acquisition system, the MIPS processor, IIC controllers, the AD video interface, LCD controller, SRAM control in this system will be embedded into the FPGA internal functional structure of Figure 1.
Platform: | Size: 515072 | Author: 陈大伟 | Hits:

[VHDL-FPGA-Verilog] VHDLyinpincaijixitong

Description: 例利用ALTIUM设计一个数字可控的混响系统，在这个系统中将把MIPS处理器、IIS控制器、SPI控制器、SRAM控制嵌入到FPGA内部实现图1的功能结构。 -Patients using the ALTIUM design a digital reverberation system, the system controllable MIPS processor, IIS controller, SPI controller, SRAM control will be embedded into the FPGA internal functional structure of Figure 1.
Platform: | Size: 847872 | Author: 陈大伟 | Hits:

[Other] fpga_pc_software

Description: 计算机组成原理课程实验使用软件，Thinpad教学机教学实验软件 实现mips代码到机器代码之间的转换 实现本机和FPGA板的通信，将机器代码送入 可在本机编写代码送入fpga板的sram中，fpga板的cpu会运行-Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine code conversion for communication between the machine and the FPGA board can be fed into the machine code written in native code into the fpga board sram in, fpga board cpu runs
Platform: | Size: 7128064 | Author: wala | Hits:

[VHDL-FPGA-Verilog] cpu_design

Description: FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Platform: | Size: 2428928 | Author: leo | Hits:

[VHDL-FPGA-Verilog] minimips_latest.tar

Description: minimalistic mips core. you can load it to any fpga.
Platform: | Size: 498688 | Author: aineko | Hits:

[VHDL-FPGA-Verilog] f32c-master

Description: FPGArduino源码，f32c：VHDL的MIPS和RISC-V指令集实现(FPGArduino source code, f32c:VHDL MIPS and RISC-V instruction set implementation)
Platform: | Size: 3957760 | Author: Peter Bee | Hits:

[assembly language] OExp13-SOC

Description: 使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用MIPS汇编编写逻辑完成的躲避球小游戏(Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game)
Platform: | Size: 12132352 | Author: 日日夜夜 | Hits:
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