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[Windows Develop] ram DL : 0: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Update : 2025-02-17 Size : 1kb Publisher : 杨艳
[VHDL-FPGA-Verilog] 基于FPGA的直接数字合成器设计 DL : 0: 1、利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、输出波形要求：在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz；在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Update : 2025-02-17 Size : 21kb Publisher : 竺玲玲
[VHDL-FPGA-Verilog] dpram_fpga DL : 0: 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
Update : 2025-02-17 Size : 2.7mb Publisher : 李伟
[Embeded-SCM Develop] fpga_ram_flash DL : 0: 一个fpga开发板的原理图，此板具有led灯、ram、flash-an fpga development board diagram, the board has led lights, ram, flash
Update : 2025-02-17 Size : 108kb Publisher : xuyang
[VHDL-FPGA-Verilog] DDR_SDRAM_Controller DL : 0: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Update : 2025-02-17 Size : 662kb Publisher : 钟方
[VHDL-FPGA-Verilog] FIFO_BEFORE DL : 0: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Update : 2025-02-17 Size : 207kb Publisher : eva
[VHDL-FPGA-Verilog] ram DL : 0: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Update : 2025-02-17 Size : 2kb Publisher : nick
[Other Embeded program] DDram DL : 0: 07全国大学生电子设计竞赛C题获奖作品FPGA外围接口双口RAM部分源码-07 National Undergraduate Electronic Design Contest winning entries C title peripheral interface FPGA dual-port RAM part of source
Update : 2025-02-17 Size : 1kb Publisher : SRY
[MiddleWare] ram DL : 0: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
Update : 2025-02-17 Size : 1kb Publisher : gcy
[VHDL-FPGA-Verilog] FPGA_two-way_IO DL : 0: FPGA Verilog,双向端口的研究,比较全,由ASSIGN和ALWAYS模块组成,测试可用-FPGA Verilog, bi-directional port studies comparing full-, and ALWAYS by ASSIGN modules, testing available
Update : 2025-02-17 Size : 113kb Publisher : 鲍纯贝
[VHDL-FPGA-Verilog] Wave_ROM DL : 0: 基于RAm的FPGA实现DDS,有测试文件-Ram realize the FPGA-based DDS, have the test paper
Update : 2025-02-17 Size : 5kb Publisher : xsj
[VHDL-FPGA-Verilog] T4_sdram_control DL : 0: verilog语言利用FPGA控制SDRAM，相信很多朋友都需要快下载吧-control FPGA Verilog language use SDRAM, believe that many of my friends need to download it faster
Update : 2025-02-17 Size : 19kb Publisher : 杜菲
[VHDL-FPGA-Verilog] memio DL : 0: 最新VHDL 模块，实现对SRAM的控制，能直接用在ALTEAR XILLIX 等 FPGA上，-Latest VHDL modules to realize the control of SRAM can be directly used for ALTEAR XILLIX such as FPGA, the
Update : 2025-02-17 Size : 7kb Publisher : 骑士
[Other] FPGA-TWO-RAM DL : 0: 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
Update : 2025-02-17 Size : 4kb Publisher : zhan
[VHDL-FPGA-Verilog] ram DL : 0: ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
Update : 2025-02-17 Size : 1.83mb Publisher : mamou
[VHDL-FPGA-Verilog] ram DL : 0: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
Update : 2025-02-17 Size : 194kb Publisher : Daisy
[Software Engineering] RAM-FPGA-FFT DL : 0: 内嵌RAM的种类，在FFT中的应用,以及仿真验证及应用-Types of embedded RAM, the FFT application
Update : 2025-02-17 Size : 123kb Publisher : Dean
[VHDL-FPGA-Verilog] actel-fpga-double-port-ram DL : 0: 基于Actel FPGA的双端口RAM设计--周立功单片机-Actel FPGA-based dual-port RAM design- ZLG MCU
Update : 2025-02-17 Size : 265kb Publisher : fei
[VHDL-FPGA-Verilog] FPGA-RAM-Verilog DL : 0: 用Verilog语言编写的FPGA，对波形数据用RAM存储-Using Verilog language FPGA, using the waveform data stored in RAM
Update : 2025-02-17 Size : 4.62mb Publisher : 何恒盛
[Other] FPGA-RAM-read-and-write-procedures DL : 0: FPGA读写RAM的程序，用FPGA实现RAM，并从单片机读写数据。-FPGA RAM read and write procedures
Update : 2025-02-17 Size : 399kb Publisher : 李恩旭

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