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[USB develop] FX2 GPIF Burst DL : 0: CY7C68013的GPIF burst源程序，主要示例GPIF BURST模式的使用-Sample GPIF burst source code for CY7C68013 how to use GPIF BURST mode.
Update : 2025-02-17 Size : 38kb Publisher : 三毛
[VHDL-FPGA-Verilog] VGA显示的FPGA实现方法 DL : 0: VGA显示的FPGA实现方法，包括原理和一个小例子。-the application of VGA display with FPGA,include theory and example
Update : 2025-02-17 Size : 83kb Publisher : 王天权
[Software Engineering] TMS320C6416-FPGA DL : 0: 一种基于TMS320C6416和FPGA的实时雷达信号模拟器设计-a TMS320C6416 and FPGA-based real-time radar signal simulator design
Update : 2025-02-17 Size : 215kb Publisher : imucc
[Embeded-SCM Develop] vhdlcodes DL : 0: FPGA/CPLD集成开发环境ISE的使用详解示例代码1-FPGA/CPLD Integrated Development Environment ISE Comments on the use of a code sample
Update : 2025-02-17 Size : 112kb Publisher : 邓志斌
[VHDL-FPGA-Verilog] pll DL : 0: fpga中pll时钟实现的源代码，可实现倍频或分频-pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Update : 2025-02-17 Size : 3kb Publisher : 张恒
[Other Embeded program] usb_out_fpga DL : 0: this is a sample about usb out transmission,it s default installation is D:\RedLogic\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying hardware and usb.-this is a sample about usb out transmission, it s default installation is D: RedLogicRCII_samples, and the software environment is quatrusII 5.0, it is usefull for studying hardware and usb.
Update : 2025-02-17 Size : 858kb Publisher : 王明
[VHDL-FPGA-Verilog] sample8 DL : 0: 运行在FPGA上的Verilog程序，实现对ADC的控制。在控制模块提供的时钟及控制信号下工作，完成模拟信号的量化和编码。
Update : 2025-02-17 Size : 293kb Publisher : 叶开
[VHDL-FPGA-Verilog] SIIGX_PCIe_Kit DL : 0: 基于SIIGX的PCIe的Kit，包含硬件原理图，pcb图，驱动，和示例代码-SIIGX based on the PCIe-Kit, includes hardware schematics, pcb map, drive, and sample code
Update : 2025-02-17 Size : 40.66mb Publisher : 林丹
[VHDL-FPGA-Verilog] isedown DL : 0: Update : 2025-02-17 Size : 1.27mb Publisher : veraking
[VHDL-FPGA-Verilog] lpf DL : 0: 实现低通采样功能的vhdl代码，可在quartus里运行。-The achievement of low-pass function vhdl sample code can be run in quartus.
Update : 2025-02-17 Size : 4kb Publisher : 桑
[VHDL-FPGA-Verilog] USB20 DL : 0: USB2_V例子工程是一个FPGA数据通过USB2.0传输到PC机的示例.-USB2_V example FPGA project is a data transmitted to the PC through the USB2.0 sample machine.
Update : 2025-02-17 Size : 371kb Publisher : 王陶
[VHDL-FPGA-Verilog] EP1C3_12_5_RSV DL : 0: 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
Update : 2025-02-17 Size : 60kb Publisher : deadtomb
[Other] digitaloscilloscope DL : 0: This digital oscilloscope takes a MCU and FPGA as the core. We made emphases on the choice of the sampling methods and the implement of equivalent sampling as a result, our design not only has the real-time sampling mode but also can reach the highest equivalent sample rate of 200 MHz using the real-time sample rate of 1 MHz, by way of random equivalent sampling. At the same time, this system has many other functions, such as 2 mV small-signal measuring, storage and re-display of waveform, measuring frequency, selective trigger edge, output of the correction signal and so on.-This digital oscilloscope takes a MCU and FPGA as the core. We made emphases on the choice of the sampling methods and the implement of equivalent sampling as a result, our design not only has the real-time sampling mode but also can reach the highest equivalent sample rate of 200 MHz using the real-time sample rate of 1 MHz, by way of random equivalent sampling. At the same time, this system has many other functions, such as 2 mV small-signal measuring, storage and re-display of waveform, measuring frequency, selective trigger edge, output of the correction signal and so on.
Update : 2025-02-17 Size : 2.08mb Publisher : 荣超群
[VHDL-FPGA-Verilog] AlteraFPGA_LM75 DL : 0: 周立功的FPGA ARM 51的板子上的温度传感器，本样例基于FPGA用Verilog写的。-Ligong weeks of the FPGA ARM 51 temperature sensors on the board, the FPGA-based sample written using Verilog.
Update : 2025-02-17 Size : 2kb Publisher : 王祥以
[SCM] sample DL : 0: 外部时钟同步，采样外部时钟，与fpga内部时钟同步-clock sample
Update : 2025-02-17 Size : 268kb Publisher : 张豪
[VHDL-FPGA-Verilog] FPGA_verilog_code_sample DL : 0: FPGA实例代码及详细注释，word 格式，对初学者很有价值-FPGA code examples and detailed notes, word format, valuable for beginners
Update : 2025-02-17 Size : 1.22mb Publisher : wanta
[VHDL-FPGA-Verilog] s3ask_ddr2 DL : 0: DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
Update : 2025-02-17 Size : 2.49mb Publisher : Joe Zhu
[VHDL-FPGA-Verilog] AD7656_Tri DL : 0: 触发AD7656进行双路采样的触发控制模块内附QUARTUS生成的bsf文件-AD7656 Dual Trigger to trigger the control module sample included QUARTUS generated bsf file
Update : 2025-02-17 Size : 660kb Publisher : 阿飞
[Other Embeded program] ARM-read-FPGA-data1.7 DL : 0: ARM读取从FPGA双口RAM读取AD采样1.7-ARM FPGA dual-port RAM read to read from the AD sample 1.7
Update : 2025-02-17 Size : 1.3mb Publisher : 张鹏
[VHDL-FPGA-Verilog] DSSS-Receiver-Sample DL : 0: FPGA 上的嵌入式系统设计实例,spartan-3e
Update : 2025-02-17 Size : 355kb Publisher : lifeng

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