Search - fpga string

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[Documents] labview_12.25 DL : 0: LabView学习资料Word版，包含：入门介绍，程序结构，数组、簇和图形，图形显示，字符串和文件，数据采集，信号分析和处理，模拟输入信号连接，公式节点语法，显示一个数据信号的步骤等。-Word version of LabView learning materials, including: Getting Started Introduction, program structure, array, cluster and graphics, graphical display, the string and documentation, data acquisition, signal analysis and processing, analog input signal connections, the formula grammar node, indicating a data signal steps.
Update : 2025-02-17 Size : 1.01mb Publisher : zhaofang
[Multimedia program] caibian DL : 0: PCM通信数据串码的形成,用FPGA产生的数据采集.-PCM communication data string to form code, using FPGA generated data collection.
Update : 2025-02-17 Size : 57kb Publisher : 高静
[VHDL-FPGA-Verilog] VHDLSourceProgramofLiquidCrystalModule DL : 0: 液晶模块显示字符串的VHDL源程序，了解液晶模块显示字符串的原理，了解如何使用FPGA对液晶模块进行显示。-VHDL Sorce Program of Using Liquid Crystal Module Demonstrates The String of Character
Update : 2025-02-17 Size : 1kb Publisher : 杨波
[VHDL-FPGA-Verilog] 1 DL : 0: 串并滤波器(FPGA源码),基于QuartusII开发设计实现的串并滤波器.-String and filter (FPGA source code), based on the achievement of development and design of QuartusII and filter string.
Update : 2025-02-17 Size : 7kb Publisher : 南才北往
[VHDL-FPGA-Verilog] hello_led DL : 0: 在FPGA开发板显示字符串,采用VHDL语言,以简单的功能说明FPGA的开发流程.-In the FPGA development board shows the string, using VHDL language, in a simple functional description FPGA-development process.
Update : 2025-02-17 Size : 6.97mb Publisher : 韩飞
[VHDL-FPGA-Verilog] p_s DL : 0: 用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
Update : 2025-02-17 Size : 5kb Publisher : cloudy
[VHDL-FPGA-Verilog] Para_to_Seril DL : 0: 用VHDL实现串并变换的程序，FPGA测试成功，正确变换。-String with VHDL implementation and transformation procedures, FPGA test successfully, the correct transformation.
Update : 2025-02-17 Size : 256kb Publisher : 陈言
[VHDL-FPGA-Verilog] LCD1602_Verilog DL : 0: 1602液晶显示字符串..用FPGA来控制1602液晶显示.-1602 LCD display with a FPGA to control the string .. 1602 LCD.
Update : 2025-02-17 Size : 876kb Publisher : 罗小明
[VHDL-FPGA-Verilog] uartfifo DL : 0: 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
Update : 2025-02-17 Size : 821kb Publisher : luoqv
[VHDL-FPGA-Verilog] 5B6B DL : 0: FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Update : 2025-02-17 Size : 603kb Publisher : 邓小虎
[VHDL-FPGA-Verilog] www DL : 0: 主要功能就是实现基于FPGA的FIR滤波器设计的串并转换。-Main function is to implement FPGA-based FIR filter design and convert the string.
Update : 2025-02-17 Size : 1kb Publisher : 王天
[VHDL-FPGA-Verilog] 1602LCD-Verilog DL : 0: 用FPGA控制在LCD1602上显示一段字符串。可以对LCD1602的控制有更深的了解-Using FPGA to control the LCD1602 display a string. LCD1602 can have a better understanding of the control
Update : 2025-02-17 Size : 292kb Publisher : 马辛未
[VHDL-FPGA-Verilog] task22constant DL : 0: 清华大学电子课程设计：Verilog语言，Quartus可以正确运行，下载到FPGA上可完成PC与FPGA一串数据的连续收发，且实现本地回环，异步串口通信-Verilog language, Quartus can be correctly downloaded to the FPGA to be completed by PC and FPGA transceivers continuous string of data, and implement local loop, asynchronous serial communication
Update : 2025-02-17 Size : 567kb Publisher : 薛芬
[VHDL-FPGA-Verilog] bsconvert DL : 0: 基于FPGA的实现数据串并转换的程序，可以把8位串行数据转换为8位并行数据，或把8位并行数据转换为8位串行数据等-FPGA-based string and data conversion procedures, can be 8-bit serial data into 8-bit parallel data, or the 8-bit 8-bit parallel data into serial data
Update : 2025-02-17 Size : 223kb Publisher : 于风
[VHDL-FPGA-Verilog] FPGA-design-ideas-and-techniques DL : 0: FPGA 设计的四种常用思想与技巧包括：乒乓操作，流水线操作，串并转换技巧，数据接口同步方法-The four commonly used FPGA design ideas and techniques include: ping-pong operation, pipelining, and convert the string technique, synchronous data interface methods
Update : 2025-02-17 Size : 106kb Publisher : salvary
[VHDL-FPGA-Verilog] the-design-of-string-out-of-register DL : 0: 利用FPGA编程-------实现“并入串出寄存器设计”-Use of FPGA programming-------incorporated into the design of string out of register
Update : 2025-02-17 Size : 304kb Publisher : 初昀
[VHDL-FPGA-Verilog] fpga-mcu DL : 0: 利用uart接口，51单片机和FPGA完成16位宽的数据通信，包括数据的幷串转换等。-Uart interface 51 of microcontroller and FPGA 16-bit wide data communications, and including Bing string of data conversion.
Update : 2025-02-17 Size : 614kb Publisher : 张朗
[VHDL-FPGA-Verilog] parallel_to_serial_conversion DL : 0: 熟悉FPGA串并转换思想，并行数据转换为串行数据输出，通过modelsim验证-Familiar FPGA string and convert ideas, parallel data into serial data output via modelsim verification
Update : 2025-02-17 Size : 5.66mb Publisher :
[Other Embeded program] piso8_ok_bingchuanzhuanhuan DL : 0: 本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)
Update : 2025-02-17 Size : 154kb Publisher : zhihuidaxian
[Com Port] d974d4330bf7 DL : 1: 这是一个非常完整的qpsk调制解调用fpga实现的工程，在工程中已经能够正常使用，使用的quartus ii 开发，使用Verilog语言，文件中还包含了各种滤波器的系数文件，还有matlab仿真文件，整个工程包含从串并变换，相位映射，到成型滤波，中通滤波，cic滤波，调制，再到解调过成的下变频，匹配滤波，载波提取，位定时，判决，整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implementation of the project, the project has been able to properly use the Quartus II development, the use of Verilog language, the file also contains the files of various filter coefficients, and MATLAB simulation files, including the entire project from the string and transform, phase mapping, molding in filtering, filtering, CIC filtering, modulation, and demodulation frequency, a matched filter, carrier extraction, timing, judgment, the whole course)
Update : 2025-02-17 Size : 12.86mb Publisher : maerzaizai

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