Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序,用verilog实现,ise7.1,不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~ Platform: |
Size: 8427520 |
Author:heartbeat |
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Description: M_UART
介绍了通用异步收发器(UART)的原理,并以可编程逻辑器件FPGA为核心控制部件,基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试,该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx Platform: |
Size: 18432 |
Author:lc |
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Description: xilinx提供的verilog_uart源码,适合做串口的人学习-Xilinx provided verilog_uart source, suitable for those who study serial Platform: |
Size: 9216 |
Author:伍迪 |
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Description: This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA. Platform: |
Size: 3072 |
Author:bhagwan |
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Description: 为增加系统稳定性,减小电路板面积,提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性,可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction. Platform: |
Size: 215040 |
Author:jalon |
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Description: xilinx官网提供的VHDL,UART串行通信模块,肯定好用,官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official Platform: |
Size: 10240 |
Author:雪尘 |
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Description: vhdl uart module. this file is used to transfer programs frm fpga xilinx spartam 3e kit to desktop pc through rs232 serial port. Platform: |
Size: 282624 |
Author:pingakshya |
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Description: 通过uart接受到一个8位的数据,在fpga ego上面用led显示出来(Receive a 8 bit data through UART and display it on FPGA ego with LED) Platform: |
Size: 712704 |
Author:怀瑾握瑜123
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