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Description: 基于FPGA的实验 UC\OS-II操作系统移植，使用SOPC软件及其配置方法，掌握其在NIOS II IDE 中的简单使用。-FPGA-based experimental UC \ OS-II operating system migration, the use of SOPC software and its configuration to grasp the NIOS II IDE in the simple use.
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Size: 1024 |
Author: 贺欧 |
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Description: 本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
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Size: 13812736 |
Author: huangshengqun |
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Description: 在FPGA硬件体系下，搭建软核处理器NIOSII，进而用NIOSII运行ucos操作系统，从硬件到软件完全实现用户定制-In the FPGA hardware system, the structures of soft-core processor NIOSII, and then run with NIOSII ucos operating system, from hardware to software to fully implement custom
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Size: 14452736 |
Author: sqf |
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Description: 根据通用船栽自动识别系统(AIS)的协议栈，给出了一种基于链路层、网络层和传输层的嵌入式系统AIS系统平台设计，详细研究了其基于ARM+FPGA的硬件设计和基于uC／OS—II操作系统的软件设计。-According to the protocol stack of tlle AIS．this paper proposes a design of the AIS system platform based on the embedded system foucs on link layer．network layer and transport
layer． and elaborates on the hardware design of ARM+FPGA and the software design founded on pLC／0S—II operating system
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Size: 323584 |
Author: jinzhi |
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Description: 在FPGA上移植uC/OS-II操做系统-Porting the FPGA uC/OS-II operating system to do
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Size: 6421504 |
Author: 朱杰作 |
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Description: 基于Altera的FPGA配置的Nios2软核，移植了uC/OS2操作系统。实现的功能包括1602字符液晶驱动，基于中断的4*4矩阵键盘检测，流水灯。所有C文件位于\software\nios2_hello_ucosii目录下。
-Embedded Nios2 System based on Altera s FPGA, with uC/OS2 RTOS transplanted. Function included: 1602 character LCD display, 4*4 matrix keyboard detection based on interruption, LED flush lights.
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Size: 14877696 |
Author: 哲 |
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Description: 基于FPGA的IIC IP硬核设计 连接UC系统，用VHDL语言书写
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Size: 36864 |
Author: 岳才奇 |
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Description: Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families.
All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer use. The MBASE address is defined as a generic and can also be easily changed and customized for customer use. In addition, this design outputs the MCF signal on a pin which can be used by the uC as a quick indication that the I2C transfer is complete.
This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects which can cause improper clocking of registers within the Stratix FPGA. If the loading of the SCL signal in the system is such that the rise and fall times are slow (>20nS), external buffers such as Schmitt Triggers will be required to interface to the
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Size: 2252800 |
Author: 我是谁 |
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Description: uc/os operation system,which is used in FPGA nios ii.
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Size: 17695744 |
Author: niukang |
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Description: uc/os operation system,which is used in FPGA nios ii.
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Size: 1024 |
Author: niukang |
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