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[VHDL-FPGA-Verilog] VGA_2c5 DL : 0: FPGA EP2C5 VGA 使用verilogHdl-VGA EP2C5 FPGA use verilogHdl
Update : 2025-02-17 Size : 300kb Publisher : liupan
[VHDL-FPGA-Verilog] VHDL-vga_core(vhdl) DL : 0: VHDL-vga_core(vhdl).rar FPGA上实现 VGA的IP（VHDL）-VHDL-vga_core (vhdl). RarFPGA realize VGA on the IP (VHDL)
Update : 2025-02-17 Size : 448kb Publisher : nanotalk
[VHDL-FPGA-Verilog] vga_lcd DL : 0: 这个是VGA的核是NOIS开发时使用的IP CORES 在FPGA的开发中使用的比较多-This is a VGA Nois nuclear development is the use of IP CORES in the FPGA used in the development of more
Update : 2025-02-17 Size : 591kb Publisher : luojie
[VHDL-FPGA-Verilog] 8080 DL : 0: EPM1270和单片机的8080通讯接口，适合单片机与CPLD之间的高速通讯，verilog语言，QuartusII环境-EPM1270 and 8080 MCU communication interface for MCU and CPLD high-speed communication between, verilog language, QuartusII environment
Update : 2025-02-17 Size : 472kb Publisher : 汉武帝
[Documents] 7670_YUV_VGA_20fps_rev_1.1 DL : 0: ov7670 VGA寄存器配置,由ov公司提供-Register ov7670 VGA configuration, provided by the ov
Update : 2025-02-17 Size : 1kb Publisher : lotus lian
[VHDL-FPGA-Verilog] hdl DL : 0: 网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。-a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.
Update : 2025-02-17 Size : 2kb Publisher : escut
[VHDL-FPGA-Verilog] vga DL : 0: 最全的FPGA VGA方面的资料及源码. VGA IPcore的Verilog代码 VGA接口设计实例及测试程序 VGA接口设计实例及测试程序(源码) VGA显示源码-FPGA VGA most comprehensive information and source code. VGA IPcore the Verilog code VGA interface design and testing procedures VGA interface design and testing procedures (source) VGA display source
Update : 2025-02-17 Size : 2.05mb Publisher : likufan
[VHDL-FPGA-Verilog] cameralink DL : 0: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Update : 2025-02-17 Size : 13kb Publisher : lilei