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[VHDL-FPGA-Verilogfpga_DO

Description: 根据ModelSim提供的命令或者Tcl/Tk语言的语法,将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中,然后直接执行这个DO文件,就可以完成整个仿真流程-According to the order provides ModelSim or Tcl/Tk language syntax, the simulation process simulation Cmd command followed by the preparation of the extension " do" macro file, and then direct the implementation of the DO file, you can complete the entire simulation process
Platform: | Size: 12288 | Author: 崔慧娟 | Hits:

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