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Description: 这是一个帧同步数据搜索模块，用于检测输入的数据流中的帧头，当检测到帧头后输出一个同步信号。
输入数据为 8bit的并行数据流，数据流中的每帧由 10 个字节组成，为 1个字
节的帧头（47H）加上 9 个字节的数据。各个字节的中间部分与时钟上升沿对齐。
每帧数据中，除帧头外的其他数据也可能为 47H。
在数据传输过程中，帧头数据有可能受到干扰而变为其他数值，因此要求输出同步信号时具有一定的容错功能。-This is a frame synchronization data search module, for detecting the input data stream in the frame header, when the detected frame header and a synchronization signal after the output. 8bit parallel input data for the data flow, data flow in each frame consists of 10 bytes for a byte frame header (47H) plus 9 bytes of data. The middle part of each byte alignment with the clock rising edge. Each frame of data, in addition to other data outside the frame header may 47H. In the data transmission process, the frame header data may be subject to interference into other values, thus requiring the output sync signal has certain fault tolerance.
Platform: |
Size: 409600 |
Author: 追月 |
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Description: 通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。-Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.
Platform: |
Size: 11264 |
Author: caobaolong |
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