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[Other resource] ERFREE_COUNTER-vhdl DL : 0: maxplus2为开发环境 vhdl编写的自由计数器程序-maxplus2 VHDL environment for the development of free counter preparation procedures
Update : 2008-10-13 Size : 12.35kb Publisher : 丁智罡
[VHDL-FPGA-Verilog] ERFREE_COUNTER-vhdl DL : 0: maxplus2为开发环境 vhdl编写的自由计数器程序-maxplus2 VHDL environment for the development of free counter preparation procedures
Update : 2025-02-17 Size : 12kb Publisher : 丁智罡
[VHDL-FPGA-Verilog] xsoc-beta-093 DL : 0: This free cpu-ip! use verilog
Update : 2025-02-17 Size : 3.19mb Publisher : 王军
[VHDL-FPGA-Verilog] VHDL_freerisc8 DL : 0: Update : 2025-02-17 Size : 258kb Publisher : 韩红
[VHDL-FPGA-Verilog] select7 DL : 0: VHDL七人表决器免费为大家服务-VHDL seven people to vote for you for free!
Update : 2025-02-17 Size : 35kb Publisher : man
[Windows Develop] 2005122512232492458 DL : 0: 本文件是关于vhdl语言的网上最近的免费ip核文件。-VHDL language on the Internet free ip recent nuclear documents.
Update : 2025-02-17 Size : 348kb Publisher : 崔战
[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code DL : 0: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Update : 2025-02-17 Size : 23kb Publisher : Jawen
[SCM] PinYin_InputMethod_C51 DL : 0: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-( 编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
Update : 2025-02-17 Size : 14kb Publisher : Jawen
[Crack Hack] ecc-0.3.16-src DL : 0: 椭圆曲线加密算法源代码,用VC编写,可以免费下载-elliptic curve encryption algorithm source code, prepared by VC can be downloaded free of charge
Update : 2025-02-17 Size : 105kb Publisher : 刘志朋
[VHDL-FPGA-Verilog] cpu86model DL : 1: 关于8086的软核fpga代码，可以直接再fpag的开发板上调试，好用而且是免费的-on the 8086 soft-core fpga code can then direct the development fpag board debugging, handy and free
Update : 2025-02-17 Size : 264kb Publisher : 赵春生
[Other] VHDL_program_design_book DL : 0: VHDL程序设计与应用，PDG图书用工具dgreader free.exe打开-VHDL design and application procedures, PDG books tools dgreader free.exe Open
Update : 2025-02-17 Size : 3.85mb Publisher : 磊
[Other] VHDL_design_express_synthesize DL : 0: VHDL设计：表示和综合（原书第2版）,使用工具dgreader free.exe打开-VHDL Design: express and synthesis (the original version 2), the use of tools to open dgreader free.exe
Update : 2025-02-17 Size : 7.87mb Publisher : 磊
[Algorithm] xfft16_beh_vhdl DL : 0: 能实现16位的快速傅立叶变化,位数可自由设定,输出斜波可调整个数-Can realize the fast Fourier 16 changes in the median can be free to set up, the output ramp adjustable number of
Update : 2025-02-17 Size : 149kb Publisher : 胡召宇
[Other] verilog_languige DL : 0: 一个关于VHDL语言的GUIDE,适合初学者使用,大家可以自由下载,不用受限,不喜欢那种形式.谢谢.-On the VHDL language GUIDE, suitable for beginners to use, everyone is free to download, not constrained, and do not like the kind of form. Thank you.
Update : 2025-02-17 Size : 4.75mb Publisher : madder
[VHDL-FPGA-Verilog] 8255_OSED DL : 0: 用VHDL语言实现可编程并行接口芯片8255，包括8255的全部功能-Using VHDL language programmable parallel interface chip 8255, including all of the features of 8255
Update : 2025-02-17 Size : 221kb Publisher : asd
[VHDL-FPGA-Verilog] RS232 DL : 0: quatus II 环境下vhdl实现RS232功能-quatus II environment realize RS232 VHDL functional
Update : 2025-02-17 Size : 427kb Publisher : 王艳华
[Other] VGALCD DL : 0: lcd控制器的源程序，可以随便使用，免费试用。不多描述。-lcd controller source code, you can not use, free trial. Not much to describe.
Update : 2025-02-17 Size : 483kb Publisher : 刘源
[VHDL-FPGA-Verilog] 4 DL : 0: 控制模块是频率计的核心所在,具有如下所述功能：对输入数据判断并输出档位信号； ——10KHZ最高位为1010，换高档，最低位为0000，小数点不亮，表无信号； ——100KHZ最高位为1010，换高档，最高位为0000，换低档测试； ——1MHZ、10MHZ同100KHZ测试档。针对不同的档位输出不同的时基信号； ——100ms时基信号，用于10KHZ档位测量 ——10ms时基信号，用于100KHZ档位测量 ——1ms时基信号，用于1MHZ档位测量 ——0.1ms时基信号，用于10MHZ档位测量 -Control module is the core of Cymometer with features as described below: The input data to determine and output stall signals - 10KHZ highest for 1010, for high-grade, the lowest for 0000, the decimal point does not shine, table-free signal ---100KHZ highest for 1010, for high-grade, the highest for 0000, for low-grade tests - 1MHZ, 10MHZ with 100KHz test file. Stalls for different output signals of different time-base - 100ms time base signal for the measurement of 10KHz stalls- 10ms time base signal for the measurement of 100KHz stalls- 1ms time base signal for 1MHz stalls Measurement- 0.1ms time base signal for the measurement of 10MHz stalls
Update : 2025-02-17 Size : 2kb Publisher : 张伯伦
[VHDL-FPGA-Verilog] 100Examples DL : 0: verilog 语言可以免费下载的程序-Verilog language can be downloaded for free procedures
Update : 2025-02-17 Size : 204kb Publisher : kerluo
[VHDL-FPGA-Verilog] 1204pointsFFT DL : 0: 1024点FFT VHDL实现,含有说明部分，自己好好理解，可自行修改-1024 point FFT VHDL realization that contain part of a good understanding of their own, they are free to modify
Update : 2025-02-17 Size : 27kb Publisher : kevin

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