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[VHDL-FPGA-Verilog] freqm

Description: 以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计，采用在一定时间内对数字脉冲计数的方法，可直接测量TTL电平的数字脉冲信号的频率、周期和脉宽。其他一些信号可经过信号预处理电路变换后测量。量程：1Hz～999999Hz 输入信号：（1）TTL电平数字脉冲信号；（2）方波/正弦波，幅度0.5~5V 显示：七段数码管显示频率（Hz）和周期/脉宽（us）控制：两个拨码开关切换三种工作模式：测频率，测周期，测脉宽-Frequency Counter realized with Altera EPM7128SLC84-15. It can measure frequecy, cycle and pulse width of TTL sigals.
Platform: | Size: 1053696 | Author: tom | Hits:

[VHDL-FPGA-Verilog] freqm

Description: a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
Platform: | Size: 12288 | Author: wangfeng | Hits:

[VHDL-FPGA-Verilog] freqm

Description: frequency multiplier
Platform: | Size: 83968 | Author: nattu | Hits:

[VHDL-FPGA-Verilog] freqm

Description: Control of a frequency meter example
Platform: | Size: 916480 | Author: aljoal | Hits:

[VHDL-FPGA-Verilog] freqm

Description: code qui nous permet de visualiser les differentes frequences
Platform: | Size: 92160 | Author: YASSINE | Hits:

[VHDL-FPGA-Verilog] freqm.verfinal

Description: 基于xlinx FPGA的频率计，顶层文件为freqm.v 可以直接仿真或烧写。通过外部选择闸门时间可实现不同量程。闸门时间有1s，0.1s，0.01s，0.001s可选。数码管显示6位数值。最高可测99M的信号输入。-Based on xlinx FPGA frequency meter, top-level file for freqm.v direct simulation or programming. External to select the gate time can be achieved The same range. The gate time of 1s, 0.1s, 0.01s, 0.001s optional. The digital display value of 6. The maximum measured 99M signal input.
Platform: | Size: 3072 | Author: 任程辉 | Hits:

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[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] freqm.verfinal

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