Description: 利用FPGA设计的可以自适应的频率计，里面有详细的文档介绍。-FPGA designs can use adaptive frequency counter, which document describes in detail. Platform: |
Size: 106496 |
Author:李庆雨 |
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Description: Clk50M_div_1HZ，调试已通过，采用计数器分频
此实验采用计数器，将板载的50MHz时钟源分频为1Hz，分频的结果以LED灯的形式显示。下载电路至FPGA后，会发现LED0会以1Hz的频率闪动。-Clk50M_div_1HZ, using counter this study, frequency counter, onboard 50MHz clock frequency of 1Hz, frequency results in the form of LED lights display. Download the circuit to the FPGA, you will find LED0 will be the frequency of 1Hz flashing. Platform: |
Size: 324608 |
Author:王晨 |
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Description: VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
-VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u Platform: |
Size: 1367040 |
Author:张学仁 |
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Description: 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompression can be directly downloaded to the DE2 board, in which the frequency of the input of the system comes with 27M clock D13 used for testing If you want to apply to other development board can reassign pin. Platform: |
Size: 615424 |
Author:予烨 |
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Description: 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能，且数据ROM 在高速条件下，占用最少的逻辑资源，设计流程最便捷，波形数据获最方便。下图是此信号发生器结构图，顶层文件SINGT.VHD 在FPGA 中实现，包含2 个部分：ROM 的地址信号发生器，由5 位计数器担任，和正弦数据ROM，拒此，ROM由LPM_ROM模块构成能达到最优设计，LPM_ROM底层是FPGA中的EAB或ESB等。地址发生器的时钟CLK的输入频率f0与每周期的波形数据点数（在此选择64 点），以及D/A输出的频率f 的关系是：f=f0/64。-Sinusoidal signal generator design, the structure of the sinusoidal signal generator consists of three parts. The data counter, or address generator, data ROM and D/A. The good performance of the sinusoidal signal generator design requirements Part 3 high-speed performance, and the ROM data in high-speed conditions, take up minimal logic resources, the design process is the most convenient, the waveform data is the most convenient. The following figure is a block diagram of this signal generator, top file SINGT.VHD is implemented in FPGA, consists of two parts: ROM address signal generator, served by the 5-bit counter, and the sine ROM reject this ROM by LPM_ROM module constitute optimal design LPM_ROM is the underlying FPGA EAB or ESB. The address generator clock CLK input frequency f0 and per period of the waveform data points selected in (64), and the relationship between D/A output frequency f is: f = f0/64. Platform: |
Size: 1825792 |
Author:吴祥 |
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Description: 本设计是基于FPGA控制的PWM信号输出系统，以EP3C5E144C8芯片为核心，通过参考信号和输入信号在计数器中的比较来实现占空比、频率可调的脉冲宽度调制信号-The design is FPGA-based control of the PWM signal output system, to EP3C5E144C8 chip as the core, to achieve adjustable duty cycle, frequency, pulse width modulation signal by the reference signal and the input signal in the counter compare Platform: |
Size: 6710272 |
Author:席晓明 |
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Description: 第一，DDS模块是一个比较常用的用数字方式实现模拟信号的方法，以前一直只用了频率控制，这一次还通过深入理解用上了相位控制，从这个角度来讲，可以用FPGA小菜一碟的实现频率和相位可控的多通道SPWM波，然后再去外加上RC滤波电路和运放电路就可以实现可控正弦波。
第二，这里的DDS模块还有产生一个可逆计数器的计数使能时钟和方向控制时钟，需要具体说说的是，如果你输出的正弦值是8位的，那么你的计数器的计数范围是在0---255---0，如果你输出的正弦值是9位的，那么你的计数器的计数范围是在0---511---0。还有，每此计数变化后（一个“数字”三角波产生），DDS中只输出一个正弦值，进行比较。-First, the DDS module is a more commonly used in digital way to realize analog signal, the method of used in frequency control, this time also by deep understanding of using phase control, from this perspective, you can use the FPGA implementation of a piece of cake of frequency and phase controlled multichannel SPWM wave, and then to plus the RC filter circuit and the op-amp circuit can realize controllable sine wave.
Second, the DDS module and create a reversible counter count can make the clock and direction control clock, need specific about is that if you output sine value is 8 bits, so is the scope of your counter counts in 0-255-0, if your output sine value is nine, so is the scope of your counter counts in 0-511-0. Also, every change after the count (a "number" triangle wave), only in the DDS output a sine value, the comparison
Platform: |
Size: 162816 |
Author:张雪亮 |
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Description: FPGA设计中，实现基准时钟的分频模块，该模块是将外围电路中所提供的50MHZ将其分频，对时钟模块作用后产生一秒一秒的时钟信号，另外对显示模块的计数器提供时钟实现显示模块的扫描功能。(The design of FPGA, the reference clock frequency module, this module is provided in the peripheral circuit of the 50MHZ frequency, the clock module generates a clock signal after a second second, also provides the clock display function module display module to scan the counter.) Platform: |
Size: 6310912 |
Author:i belive |
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