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Description: 在软件无线电中半带滤波器的设计与实现，半带滤波器实现的是2的幂次的抽取或插值。
-In software radio half-band filter design and realization of half-band filter is the realization of 2-power extraction or interpolation.
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Size: 246784 |
Author: 岑楠 |
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Description: This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).
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Size: 22528 |
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Description: 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
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Size: 18432 |
Author: pll |
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Description: 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T receiver machine multi-rate DDC module, and the simulation in the FPGA implementation. Numerical oscillation in the complex mixer module, based on the input signals of different bandwidths (6M/8MHz) choose a different group of complete decimation filter extracted factor 3 or 4 of the multi-rate processing tasks, using two half-band filter (HBF) cascade to complete four times decimation filter, single-stage Chennai Nyquist filter to complete three times the decimation filtering.
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Size: 309248 |
Author: 王楚宏 |
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Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
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Size: 201728 |
Author: jiang |
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