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[SourceCode] HDB3编码 DL : 0: 本程序是关于通信原理的HDB3编码及其功率谱密度
Update : 2010-12-13 Size : 1.4kb Publisher : 393909084@qq.com
[VHDL-FPGA-Verilog] hdb3 decoder DL : 0: 我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Update : 2025-02-17 Size : 117kb Publisher : 王薇
[Algorithm] HDB3 DL : 0: 源于老师的作业,实现将01代码转化成HDB3码,另外还有用VHDL语言编的,不过我这没有-teachers from the operations, achieving 01 HDB3 code into the code, as well as using VHDL series, but I am not
Update : 2025-02-17 Size : 38kb Publisher : 王原
[JSP/Java] HDB3 DL : 0: 此程序的功能是根据数字基带码可以进行AMI码，HDB3码转换，并画出相应的波形。-The function of this procedure is based on the number of base-band code can be AMI code, HDB3 code-switching, and draw the corresponding waveform.
Update : 2025-02-17 Size : 9kb Publisher : 袁辉
[Other Embeded program] hdb3 DL : 0: hdb3的发送端源代码，采用verilog可综合格式书写。已经在多款fpga和cpld芯片成功综合实现。-HDB3 sending client source code, Verilog can be used to write an integrated format. Has been in several FPGA and CPLD chip integrated to achieve success.
Update : 2025-02-17 Size : 1kb Publisher : frankey
[VHDL-FPGA-Verilog] hdb3 DL : 0: 实现通信过程中的hdb3转换,是通信原理课程中很重要的部分.-Realize HDB3 communication in the process of conversion, is the Communication Theory course a very important part.
Update : 2025-02-17 Size : 1kb Publisher : 王晓鹏
[VHDL-FPGA-Verilog] hdb3 DL : 0: hDB3的编解码模块是在maxplusII 下验证过的并且下到片子中都正确 -HDB3 codec module is tested under maxplusII and down to the film are correct
Update : 2025-02-17 Size : 3kb Publisher : duan
[VHDL-FPGA-Verilog] HDB3 DL : 0: 实现HDB3编码，文件清晰，执行效率高。有每条语句的说明，阅读简单。-Realize HDB3 coding, document clear, the implementation of high efficiency. Each statement has a note, reading simple.
Update : 2025-02-17 Size : 2kb Publisher : 王青
[ELanguage] hdb3 DL : 0: 在VHDL平台上实现HDB3编码的源程序已调试完-In VHDL realize HDB3 encoding platform has been the source debugging End
Update : 2025-02-17 Size : 1kb Publisher : 王晓鹏
[VHDL-FPGA-Verilog] hdb3 DL : 0: HDB3码的VHDL实现共三个模块：插入V、插入B以及单双极性变换-VHDL code HDB3 realize a total of three modules: Insert V, insert B, as well as single-and double-polar transform
Update : 2025-02-17 Size : 1kb Publisher : Xingzhi
[Communication] HDB3 DL : 0: 开发环境:VC++ 通信原理练习:HDB3-Development Environment: VC++ Communication Theory to practice: HDB3
Update : 2025-02-17 Size : 1kb Publisher : Saterday
[matlab] HDB3 DL : 0: HDB3码的编码，图形，功率谱密度。用于通信原理教学等-Code HDB3 coding, graphics, power spectral density. Communication Theory for teaching
Update : 2025-02-17 Size : 1kb Publisher : 连自锋
[Other] HDB3 DL : 0: 通信原理HDB3码的仿真程序MATLAB中开发-Communication Theory HDB3 code simulation program developed in MATLAB
Update : 2025-02-17 Size : 1kb Publisher : rjs
[VHDL-FPGA-Verilog] HDB3 DL : 0: hdb3的编解码实现，用c表述的实际应用性不强，只为说明原理。-HDB3 codec realize, with the practical application of c expression is not strong, only to illustrate the principle.
Update : 2025-02-17 Size : 188kb Publisher : lixingjian
[VHDL-FPGA-Verilog] hdb3 DL : 0: vhdl语言实现的hdb3编解码的功能，已完成调试。-vhdl
Update : 2025-02-17 Size : 1kb Publisher : 王英超
[Software Engineering] HDB3 DL : 0: 实现HDB3编码,使用VHDL语言，-1用01表示，1用10表示，0用00表示。-The realization of HDB3 encoding, the use of VHDL language, 01 indicated by-1, 1, 10, said that the 0 with 00.
Update : 2025-02-17 Size : 267kb Publisher : zhangzhen
[ELanguage] hdb3 DL : 0: 基于vhdl的hdb3编译码器的设计与实现-hdb3
Update : 2025-02-17 Size : 231kb Publisher : fdfilkj
[VHDL-FPGA-Verilog] HDB3 DL : 0: VHDL语言编写的HDB3码的编译码模块-VHDL language code HDB3 codec module
Update : 2025-02-17 Size : 429kb Publisher : 容蓉
[VHDL-FPGA-Verilog] HDB3 DL : 0: 用VerilogHDL实现了从NRZ码到HDB3码的编码过程-NRZ code to HDB3 code using VerilogHDL
Update : 2025-02-17 Size : 1kb Publisher : 谈钒
[MiddleWare] HDB3 DL : 0: HDB3编码源程序,实现该编码的程序，编码源程序。vc++环境的。-hdb3 bian ma yuan cheng xu.shi xian hdb3 de bian ma .ji yu vc++ shi yan huan jing de cheng xu.
Update : 2025-02-17 Size : 265kb Publisher : 麻麻

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