Description: 浅显易懂的vrilogHDL的程序,可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly. Platform: |
Size: 158720 |
Author:陈浩东 |
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Description: 用Verilog HDL 语言写的在LCD液晶上显示文字的源程序-with Verilog HDL write on the LCD display text of the source Platform: |
Size: 423936 |
Author:yhr |
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Description: Verilog HDL编写的总线功能模型,十分有用,需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download Platform: |
Size: 2048 |
Author:wyl |
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Description: 本原码是基于Verilog HDL语言编写的,实现了SPI接口设计,可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulation. Platform: |
Size: 1024 |
Author:jevidyang |
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Description: 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码,但是他自己说有问题,但是不知道怎么改。我大概看了一下,发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably watched and found ideas is quite a mess. So I wrote on their own code and string conversion. Platform: |
Size: 1024 |
Author:ZHAOBOO |
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Description: Verilog HDL的程式,上網找到SPI程式,
vspi.v這程式相當好用可用來接收與傳送SPI,並且寫了一個傳輸信號測試,spidatasent.v這程式就是傳送的資料,分別為00 66... 01 77...... 02 55這樣的資料,並透過MAX+PULS II軟體進行模擬,而最外層的程式是test_createspi.v!-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v! Platform: |
Size: 145408 |
Author:Rick |
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Description: 基于Verilog HDL的SPI代码,可在FPGA上实现SPI接口,请大家参考-Verilog HDL based on the SPI code, implementation in FPGA on SPI interface, please refer to Platform: |
Size: 1024 |
Author:treefan.liang |
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