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[Other resource] HDLC

Description: HDLC链路层协议的CRC校验.HDLC使用16位CRC校验。使用的多项式是：x16+x12+x5+x0
Platform: | Size: 1553 | Author: 李洪臣 | Hits:

[Communication] CRC16_D8.v

Description: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试
Platform: | Size: 915 | Author: 张纪强 | Hits:

[Other resource] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块
Platform: | Size: 1064 | Author: 张纪强 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言
Platform: | Size: 1127 | Author: 刘彻 | Hits:

[Embeded-SCM Develop] tdm_hdlc

Description: 在大型通信系统（机架插板式）中多块单板通过TDM总线，利用HDLC协议实现内部通讯的源码-in large communication system (Plug-rack), plus veneer through TDM bus, HDLC protocol using internal communications FOSS
Platform: | Size: 113664 | Author: hubinglong | Hits:

[source in ebook] HDLC

Description: HDLC链路层协议的CRC校验.HDLC使用16位CRC校验。使用的多项式是：x16+x12+x5+x0-HDLC link layer protocol of the CRC checksum. HDLC using 16-bit CRC checksum. Polynomial is used: x16+ X12+ X5+ X0
Platform: | Size: 1024 | Author: 李洪臣 | Hits:

[Communication] CRC16_D8.v

Description: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试-Ccitt crc checksum completed. HDLC protocol controller for the preparation of the CRC checksum module. Through the simulation test
Platform: | Size: 1024 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[Crack Hack] crc

Description: crc校验 包括原理文件和说明 另附有一个crc16的c程序函数和crc32的vc项目文件-CRC checksum, including the principle of documents and a note attached CRC16 function of c procedures and CRC32 of vc project documents
Platform: | Size: 2399232 | Author: 梁健 | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] HDLC_crc

Description: 与地铁牵引系统通信的HDLC数据的CRC程序-Communication with the MTR traction system HDLC data CRC program
Platform: | Size: 2048 | Author: 文梁 | Hits:

[VHDL-FPGA-Verilog] hdlc_latest[1]

Description: HDLC解码控制，包括CRC校验，可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
Platform: | Size: 573440 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] hdlc_rs

Description: 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual process
Platform: | Size: 6144 | Author: 周宽裕 | Hits:

[Windows Develop] hdlc

Description: HDLC——面向比特的同步协议：High Level Data Link Control（高级数据链路控制规程）。 HDLC是面向比特的数据链路控制协议的典型代表，该协议不依赖于任何一种字符编码集；数据报文可透明传输，用于实现透明传输的“0比特插入法”易于硬件实现；全双工通信，有较高的数据链路传输效率；所有帧采用CRC检验，对信息帧进行顺序编号，可防止漏收或重份，传输可靠性高；传输控制功能与处理功能分离，具有较大灵活性。-failed to translate
Platform: | Size: 109568 | Author: 赵庸 | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] crc16

Description: Crc校验程序，用于HDLC通信里面和其他的crc校验的代码，是crc16的-Crc verification procedures for the inside and other HDLC communication crc check code is the crc16 of the
Platform: | Size: 1024 | Author: 网报 | Hits:

[Windows Develop] HHDLLCzipD

Description: HDLC链路层协议的CRC校验.HDLC使用16位CRC校校验。使用的多项式是：x16+x12+x5+x0 已通过测试。 -The CRC of the HDLC link layer protocol. HDLC 16 CRC school checksum. The polynomial used is: by testing x16+x12+x5+x0.
Platform: | Size: 1024 | Author: 分开 | Hits:

[Communication-Mobile] HDLC

Description: 实现hdlc收发控制，包括0x7e帧头检索、数据整理、crc校验等(HDLC transceiver control, including 0x7e header retrieval, data collation, CRC checksum)
Platform: | Size: 95232 | Author: whyisme | Hits:

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