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[
VHDL-FPGA-Verilog
]
EPP
Description:
并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
Platform:
|
Size:
1024
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Author:
陈刚
|
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Search - how to epp fpga vhdl