Search - i2c in altera

[Embeded-SCM Develop] i2c_IP

Description: altera 的i2c ip核，可直接调用在quartus中把库指向文件位置就可-altera the i2c ip nuclear, can be directly called in the Quartus point in the database file location can be
Platform: | Size: 7168 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] I2C_auto_config

Description: 这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过-This is a VHDL language used to describe auto-configuration of the I2C module, the use of the I2C from opencores.org nucleus, the cyclone in the altera-chip debugging through
Platform: | Size: 7168 | Author: wgy | Hits:

[VHDL-FPGA-Verilog] IIC_bus

Description: 基于ALTERA公司的NIOSII的I2C总线传输应用设计-NIOSII based on ALTERA s application of the I2C bus transmission design
Platform: | Size: 13466624 | Author: 王超 | Hits:

[VHDL-FPGA-Verilog] src

Description: i2c module. i test it on Altera FPGA.
Platform: | Size: 3072 | Author: almondeo | Hits:

[VHDL-FPGA-Verilog] nios

Description: altera ep2c8V2 开发实例 timer uart I2C key interrupt 等-altera ep2c8V2 examples timer uart I2C key interrupt etc.
Platform: | Size: 11765760 | Author: chris | Hits:

[VHDL-FPGA-Verilog] 61EDA

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案，针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera' s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of
Platform: | Size: 179200 | Author: 李明 | Hits:

[VHDL-FPGA-Verilog] I2C

Description: i2c总线的工程实现，可以用在altera环境下验证-i2c bus project implementation can be used in altera verification environment
Platform: | Size: 75776 | Author: 韩向超 | Hits:

[VHDL-FPGA-Verilog] I2C

Description: I2C/IIC 总线接口驱动，在Altera和Xilinx的FPGA上跑过，Verilog编写，Craftor原创。V1.1。代码中还包含了24C02的读写测试程序，可直接用。-I2C/IIC Bus Driver, written in Verilog, v1.1. By Craftor
Platform: | Size: 2048 | Author: Craftor | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 本源代码中用Verilog HDL语言编写了I2C的顶层及子模块文件，详细完整，并在Altera实验板上得以验证-primitive code discribe the I2C s function using the Verilog HDL language, the code are particular and integrity,moreover it has been validated in the altera FPGA and passed
Platform: | Size: 18432 | Author: 蔡德胜 | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案，针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of
Platform: | Size: 4064256 | Author: looksky | Hits:

[VHDL-FPGA-Verilog] AudioVideoConfig

Description: 实现音频和视频器件的配置。器件使用的使Altera FPGA，配置方式使用乐I2C接口。-The configuration of audio and video devices. The device used in Altera FPGAs, configured to use the music I2C interface.
Platform: | Size: 1207296 | Author: qiumh | Hits:

[SCM] I2c

Description: 单片机可用的I2C接口代码，已在altera Nios II验证通过-I2C interface code, has been verified in the NiosII Altera
Platform: | Size: 6144 | Author: liven | Hits:

[VHDL-FPGA-Verilog] i2cBUS

Description: Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer use. The MBASE address is defined as a generic and can also be easily changed and customized for customer use. In addition, this design outputs the MCF signal on a pin which can be used by the uC as a quick indication that the I2C transfer is complete. This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects which can cause improper clocking of registers within the Stratix FPGA. If the loading of the SCL signal in the system is such that the rise and fall times are slow (>20nS), external buffers such as Schmitt Triggers will be required to interface to the
Platform: | Size: 2252800 | Author: 我是谁 | Hits:

[VHDL-FPGA-Verilog] i2c_master_ip_for_nios

Description: i2c master ip for altera nios, add in qsys
Platform: | Size: 218112 | Author: kevinfeng83 | Hits:

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[Embeded-SCM Develop] i2c_IP

[VHDL-FPGA-Verilog] I2C_auto_config

[VHDL-FPGA-Verilog] IIC_bus

[VHDL-FPGA-Verilog] src

[VHDL-FPGA-Verilog] nios

[VHDL-FPGA-Verilog] 61EDA

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] I2C

[VHDL-FPGA-Verilog] DE2_TV

[VHDL-FPGA-Verilog] AudioVideoConfig

[SCM] I2c

[VHDL-FPGA-Verilog] i2cBUS

[VHDL-FPGA-Verilog] i2c_master_ip_for_nios

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