Search - i2c slave verilog

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[SCM] ADuC814_I2C DL : 0: ADI公司，型号为ADuC814的单片机的I2C总线通讯程序源码，含MASTER和SLAVE两种方式-ADI, model for the SCM ADuC814 I2C bus communication program source code, including the MASTER and SLAVE two ways
Update : 2025-02-17 Size : 5kb Publisher : duck
[Other Embeded program] I2C_slave_model DL : 0: 完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考 -integrity of the I2C slave model and spec are attached, want to use Verilog for the development of such transmission of reference
Update : 2025-02-17 Size : 221kb Publisher : 李寧
[VHDL-FPGA-Verilog] I2CSlave DL : 0: Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
Update : 2025-02-17 Size : 1kb Publisher : lzy
[VHDL-FPGA-Verilog] i2c_slave_model_verilog DL : 0: 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
Update : 2025-02-17 Size : 2kb Publisher : hxwf801
[Com Port] i2c_slave DL : 0: 一个好用的经过FPGA验证的i2c_slave verilog代码。-After a useful FPGA proven i2c_slave verilog code.
Update : 2025-02-17 Size : 4kb Publisher : 王晓琴
[VHDL-FPGA-Verilog] I2Cslave DL : 0: i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试-i2c slave, this is the receiving end I2CBUS source code, from VERILOG languages, through integrated and debug
Update : 2025-02-17 Size : 1kb Publisher : Xiaoyang Wang
[VHDL-FPGA-Verilog] i2c_slave DL : 0: I2c中通信的从机发送和接收信息的Verilog程序测试模块，用Modelsim仿真通过-I2C communication from machine to send and receive information Verilog module test procedures, using ModelSim simulation through
Update : 2025-02-17 Size : 5kb Publisher : Tomersun
[VHDL-FPGA-Verilog] i2c_Sample DL : 0: verilog在cpld上实现i2c主从设备通讯功能-Verilog CPLD achieved in i2c master-slave communication equipment
Update : 2025-02-17 Size : 702kb Publisher : nedazq
[VHDL-FPGA-Verilog] i2c_p_altera DL : 0: altera i2c slave ip核verilog 编写-altera i2c slave ip to prepare nuclear Verilog
Update : 2025-02-17 Size : 1.51mb Publisher : 1984taozi
[ARM-PowerPC-ColdFire-MIPS] I2C DL : 0: IIC控制器的verilog实现，通过mcu接口对iic slave器件进行控制-IIC controller Verilog realize
Update : 2025-02-17 Size : 340kb Publisher : yu
[VHDL-FPGA-Verilog] I2C_receiver DL : 0: 自己写的一个i2c slave的模块，verilog，已经通过验证，可以写可以读，希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
Update : 2025-02-17 Size : 2kb Publisher : lj
[VHDL-FPGA-Verilog] i2c_master_slave_core DL : 0: I2C master/slave IP core
Update : 2025-02-17 Size : 2.08mb Publisher : zhanglh
[VHDL-FPGA-Verilog] I2C_Slave DL : 0: I2C从设备（Slave） Verilog 代码、设计文档和使用文档，简单、适用：很方便修改工作频率，自定义寄存器接口。-I2C slave (Slave) Verilog code, design documents and user guide, simply to apply: the frequency of easy modification, customized register interface.
Update : 2025-02-17 Size : 583kb Publisher : QinZhujun
[VHDL-FPGA-Verilog] IIC_slave_code DL : 0: I2C slave 代码，可以完成从机功能-about I2C slave code about I2C slave code
Update : 2025-02-17 Size : 181kb Publisher : qinjuanyan
[Embeded-SCM Develop] i2c DL : 0: 这是一个I2C总线设计,同时包括了仿真验证环境，可以同过主机从机验证该I2C设计功能-this is a i2c bus verilog design ,also including the simulation environment.
Update : 2025-02-17 Size : 173kb Publisher : rsd
[VHDL-FPGA-Verilog] I2C DL : 0: iic verilog 从机程序包含iic Verilog的主模块，控制模块和io寄存器模块-iic Verilog slave
Update : 2025-02-17 Size : 342kb Publisher : ppddxxx
[VHDL-FPGA-Verilog] i2c DL : 0: I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
Update : 2025-02-17 Size : 13kb Publisher : dingyy
[VHDL-FPGA-Verilog] i2c DL : 0: i2c verilog描述商用级别可直接用于芯片设计/fpga设计-i2c slave verilog code, full tested
Update : 2025-02-17 Size : 19kb Publisher : sdwsh
[VHDL-FPGA-Verilog] I2C DL : 0: FPGA I2C verilog代码，代码有注释。-FPGA I2C slave verilog code,with code remark.
Update : 2025-02-17 Size : 337kb Publisher : john
[VHDL-FPGA-Verilog] I2C_slaver_verison3.0 DL : 0: I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
Update : 2025-02-17 Size : 2mb Publisher : wenxulyu

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