Search - i2c verilog master

Search - i2c verilog master - List

[Com Port] i2c_master DL : 1: 一个好用的I2C接口master的verilog程序。
Update : 2008-10-13 Size : 4.04kb Publisher : 王晓琴
[Windows Develop] i2c_master_verilog DL : 0: i2c master code for verilog-i2c master code for Verilog
Update : 2025-02-17 Size : 242kb Publisher : zhang chi
[VHDL-FPGA-Verilog] i2c_slave_model_verilog DL : 0: 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
Update : 2025-02-17 Size : 2kb Publisher : hxwf801
[Com Port] i2c_master DL : 0: 一个好用的I2C接口master的verilog程序。 -A master-to-use interface for Verilog I2C procedures.
Update : 2025-02-17 Size : 4kb Publisher : 王晓琴
[VHDL-FPGA-Verilog] i2c_master_bit_ctrl DL : 0: 该代码用硬件描述语言Verilog系统地描述了I2C总线接口的位比特主控转换模型。对学习FPGA和I2C总线接口有极大地帮助。-The code used Verilog hardware description language description of the system bus interface I2C control bit bit-switching model. Learning I2C bus interface FPGA and a great help.
Update : 2025-02-17 Size : 2kb Publisher : fengxinya
[VHDL-FPGA-Verilog] i2c_Sample DL : 0: verilog在cpld上实现i2c主从设备通讯功能-Verilog CPLD achieved in i2c master-slave communication equipment
Update : 2025-02-17 Size : 702kb Publisher : nedazq
[VHDL-FPGA-Verilog] I2C DL : 0: 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
Update : 2025-02-17 Size : 207kb Publisher : zbs
[Embeded-SCM Develop] i2c_core DL : 0: I2C core 及testbench（verilog）-I2C core and testbench [verilog]
Update : 2025-02-17 Size : 20kb Publisher : xiaoheng
[Embeded-SCM Develop] i2_cmaster DL : 0: verilog HDL i2c主机代码-verilog HDL i2c host code
Update : 2025-02-17 Size : 1kb Publisher : 李爱国
[VHDL-FPGA-Verilog] I2C DL : 0: I2C主机端模块具有avalon-MT总线接口可挂载在Altera soc系统之上使NiosII处理器具备I2C通信能力模块由Verilog HDL编写并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This module is written with Verilog HDL and has been tested on a Cyclone II FPGA
Update : 2025-02-17 Size : 6kb Publisher : magic_andy
[Shell api] i2cslave_latest.tar DL : 0: hi this is i2c master in verilog
Update : 2025-02-17 Size : 1.24mb Publisher : praveen
[VHDL-FPGA-Verilog] I2C_slaver DL : 0: I2C从端，用于接收master的控制信号 verilog-I2C from the side, for receiving master control signal verilog
Update : 2025-02-17 Size : 2kb Publisher : zhangxinggang
[VHDL-FPGA-Verilog] i2c DL : 0: I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
Update : 2025-02-17 Size : 13kb Publisher : dingyy
[VHDL-FPGA-Verilog] I2C-Master-_-Slave-Core DL : 0: 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
Update : 2025-02-17 Size : 2.08mb Publisher : 郭天然
[VHDL-FPGA-Verilog] module-i2c DL : 0: I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NE-I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NEEDED
Update : 2025-02-17 Size : 9kb Publisher : max
[VHDL-FPGA-Verilog] Opencores_i2c DL : 0: 该程序主要详细描述了I2C的功能verilog实现,对学习verilog和I2C有很大帮助-The main program features a detailed description of I2C verilog implementation of the study of great help to verilog and I2C
Update : 2025-02-17 Size : 212kb Publisher : jiangpeng
[VHDL-FPGA-Verilog] i2c_verilog DL : 0: i2c master controller
Update : 2025-02-17 Size : 91kb Publisher : aydinmustafa09
[Other] i2c_master_module DL : 0: i2c接口的fpga实现，工作在master模式下，verilog(The FPGA implementation of the I2C interface, working in the master mode, verilog)
Update : 2025-02-17 Size : 2kb Publisher : blink_liao
[VHDL-FPGA-Verilog] apbi2c-master DL : 0: apb转i2c verilog 实现(APB bus interface to I2C bus interface)
Update : 2025-02-17 Size : 435kb Publisher : AyanamiC
[VHDL-FPGA-Verilog] i2c_verilog DL : 0: 主要包含i2c的master、slave模块，和一个简单的仿真sim文件(It mainly includes I2C master, slave module, and a simple SIM file)
Update : 2025-02-17 Size : 5kb Publisher : 时光乄星河

« 12 3 »