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Description: i2c从设备的源码,VHDL语言写的,有疑问请eMail:feng_er_cn@163.com-i2c-source from the equipment, VHDL language, and have questions, please eMail: feng_er_cn@163.com
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Size: 17408 |
Author: 宋大业 |
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Description: I2C Slave module
The module contains N accessable Registers
when in read Process, all Registers are read at a time
when in write Process, only the addressed register are Writeable.
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Size: 2048 |
Author: 李全 |
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Description: I2c中通信的从机发送和接收信息的Verilog程序测试模块,用Modelsim仿真通过-I2C communication from machine to send and receive information Verilog module test procedures, using ModelSim simulation through
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Size: 5120 |
Author: Tomersun |
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Description: verilog在cpld上实现i2c主从设备通讯功能-Verilog CPLD achieved in i2c master-slave communication equipment
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Size: 718848 |
Author: nedazq |
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Description: iic总线控制器VHDL实现
-- VHDL Source Files:
i2c.vhd -- top level file
i2c_control.vhd -- control function for the I2C master/slave
shift.vhd -- shift register
uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
upcnt4.vhd -- 4-bit up counter
i2c_timesim.vhd -- post-route I2C simulation netlist
-IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
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Size: 889856 |
Author: benny |
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Description: I2C slave可以作動,請使用
如果有問題請再讓我知道,Thank you
-I2C slave can be used for moving, use if there are problems please let me know, Thank you
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Size: 848896 |
Author: mika |
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Description: 来自opencore网站的I2C总线模块,经过验证可以使用-Opencore site from the I2C bus module, you can use a proven
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Size: 1355776 |
Author: 伍波 |
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Description: IIC控制器的verilog实现,通过mcu接口对iic slave器件进行控制-IIC controller Verilog realize
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Size: 348160 |
Author: yu |
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Description: I2C slave for FPGA and CPLD.
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Size: 1024 |
Author: DAVI |
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Description: I2C to 8-bit Parallel Bus Slave Design
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Size: 3072 |
Author: Victor |
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Description: 自己写的一个i2c slave的模块,verilog,已经通过验证,可以写可以读,希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
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Size: 2048 |
Author: lj |
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Description: I2C master/slave IP core
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Size: 2180096 |
Author: zhanglh |
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Description: 已经验证过的I2C,slave的IP,core,从一开源网站下载的,代码写的非常好,节省了FPGA的资源,比起以往的slave的CORE,这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, the CORE reduce the use of registers.
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Size: 3072 |
Author: 老牛 |
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Description: I2C slave端。可支持1带多。本人已经过调试,确认是可用的。-I2C slave side. Can support more than one band. I have been debugging, sure there is available.
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Size: 1024 |
Author: 洛空奇 |
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Description: I2C 从设备通讯程序,用于I2C 硬件设计-I2C slave communication program, used to for I2C HW design
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Size: 3072 |
Author: Watt Song |
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Description: iic verilog 从机程序
包含iic Verilog的主模块,控制模块和io寄存器模块-iic Verilog slave
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Size: 350208 |
Author: ppddxxx |
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Description: i2c slave for i2c control slave block-i2c slave
Platform: |
Size: 3072 |
Author: wanttofuk |
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Description: i2c master slave vhdl code
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Size: 4562944 |
Author: abul |
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Description: 用verilog 实现的 iic 总线编程,包括master,和slave的编程,很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
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Size: 2181120 |
Author: 郭天然 |
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Description: i2c master slave VHDL code
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Size: 4096 |
Author: budavarapu
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