Search - i2s verilog

Search - i2s verilog - List

[VHDL-FPGA-Verilog] I2S DL : 0: 这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
Update : 2025-02-17 Size : 1.51mb Publisher : 孙浩
[Books] I2S DL : 0: I2S（Inter-IC Sound Bus）是飞利浦公司为数字音频设备之间的音频数据传输而制定的一种总线标准。在飞利浦公司的I2S标准中，既规定了硬件接口规范，也规定了数字音频数据的格式。
Update : 2025-02-17 Size : 53kb Publisher : draking
[VHDL-FPGA-Verilog] DE2_i2sound DL : 0: Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。-Verilog code, suitable for beginners to learn, is based on the DE2 platform code.
Update : 2025-02-17 Size : 29kb Publisher : wang
[Other] i2s_rel1_2 DL : 0: I2S verilog HDL code including test environment
Update : 2025-02-17 Size : 268kb Publisher : richman
[VHDL-FPGA-Verilog] spitoi2s3 DL : 0: spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
Update : 2025-02-17 Size : 5kb Publisher : steny
[VHDL-FPGA-Verilog] SPItoI2S DL : 0: 该文件是I2S 转 SPI的Verilog的源代码，可以在此基础上修改成自己的应用代码-The file is transferred SPI, I2S Verilog source code, you can change the basis of their application code into
Update : 2025-02-17 Size : 108kb Publisher : andy
[VHDL-FPGA-Verilog] Verilog_cpu-_example DL : 0: 想用verilog进行CPU搭建的同学过来围观啦~-Want to use verilog for students to build over the crowd CPU 啦 ~
Update : 2025-02-17 Size : 345kb Publisher : 邵文熙
[VHDL-FPGA-Verilog] I2S DL : 0: 用verilog实现的 I2S 源码，可以直接通过Quartus运行-I2S implementation by verilog source code can be run directly through the Quartus ~ ~
Update : 2025-02-17 Size : 658kb Publisher : 张哲
[VHDL-FPGA-Verilog] I2S DL : 0: 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
Update : 2025-02-17 Size : 1kb Publisher : Wang Xue
[VHDL-FPGA-Verilog] iis DL : 0: I2S RTLs 很好的程序,已经成功通过验证和测试-I2S verilog RTLs, very easy to read
Update : 2025-02-17 Size : 15kb Publisher : liwei039
[VHDL-FPGA-Verilog] I2S-Serial-communication DL : 0: 这是I2S总线接口的Verilog实现源代码，包含了计数、左右通道选择、串行转并行等功能。-This is a Verilog I2S bus interface source code, including the count, about channel selection, serial to parallel functions.
Update : 2025-02-17 Size : 4.81mb Publisher : 小林
[VHDL-FPGA-Verilog] i2s_input DL : 0: 基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真-FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment
Update : 2025-02-17 Size : 39kb Publisher : yuda
[VHDL-FPGA-Verilog] i2s_dome2 DL : 0: 音频接口I2S的Verilog实现， -Audio port of Verilog
Update : 2025-02-17 Size : 2kb Publisher : ZHU
[VHDL-FPGA-Verilog] i2s_interface DL : 0: verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
Update : 2025-02-17 Size : 264kb Publisher : 落叶无情1992
[VHDL-FPGA-Verilog] i2s DL : 1: 用Verilog实现的i2s功能，支持24bit的左右声道接收和发送。左对齐，延迟1拍。(I2S module, Verilog I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK)
Update : 2025-02-17 Size : 8kb Publisher : zlh840
[Other] i2s_top DL : 0: i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)
Update : 2025-02-17 Size : 2kb Publisher : blink_liao