Search - idct vhdl

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[Graph program] DCT-vhdl DL : 2: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现
Update : 2008-10-13 Size : 10.46kb Publisher : liujl
[Algorithm] dct_p DL : 0: 这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.-VHDL (hardware description language) wrote a two-dimensional 8* 8 discrete cosine transform (D CT) and the anti-transform (IDCT). fully synchronous design, low gate count. can be used for multimedia and print applications.
Update : 2025-02-17 Size : 32kb Publisher : citybus
[VHDL-FPGA-Verilog] DCT_vhdl DL : 0: IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesizable
Update : 2025-02-17 Size : 10kb Publisher : 陈朋
[Graph program] DCT-vhdl DL : 0: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Update : 2025-02-17 Size : 10kb Publisher : liujl
[Documents] DCT DL : 0: 一种改进的一维DCT方案设计与实现,采用VHDL硬件语言描述,DCT以及IDCT-An improved one-dimensional program design and realization of DCT using VHDL hardware description language, DCT and IDCT
Update : 2025-02-17 Size : 306kb Publisher : 小金
[VHDL-FPGA-Verilog] erweiDCT DL : 0: 一种改进的一维DCT方案设计与实现,采用VHDL实现,DCT以及IDCT-A one-dimensional DCT to improve program design and implementation using VHDL realize, DCT and IDCT
Update : 2025-02-17 Size : 126kb Publisher : 小金
[2D Graphic] 17655_samples DL : 0: aan.cpp - 2d idct using aan algorithm ANN 算法-aan.cpp- 2d idct using aan algorithm ANN algorithm
Update : 2025-02-17 Size : 11kb Publisher :
[Graph program] dct DL : 0: this si Arithmetic core,it contains FreeDCT-L and FreeDCT-M.FreeDCT-L is a low power architecture 1-Dimensional 8-point DCT/IDCT core.FreeDCT-M is a moderate speed 1-Dimensional IDCT core
Update : 2025-02-17 Size : 846kb Publisher : lilei
[VHDL-FPGA-Verilog] dct DL : 0: 2维DCt源码，可以实现8乘8点数据的2维DCT变换 -2-D DCT-source, you can realize 8 x 8 data 2-D DCT transform
Update : 2025-02-17 Size : 5kb Publisher : jz
[VHDL-FPGA-Verilog] 8x8IDCT DL : 0: 8x8 iDCT verilog code 一次輸入八個點-8x8 iDCT verilog code once the importation of eight points
Update : 2025-02-17 Size : 7.92mb Publisher : Emuil
[VHDL-FPGA-Verilog] DCT_IDCT DL : 0: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Update : 2025-02-17 Size : 29kb Publisher : caesar
[Graph program] xapp208 DL : 0: xilinx 基于查找表方法实现的IDCT的verilog源码-Xilinx LUT-based method to achieve the IDCT of the Verilog source code
Update : 2025-02-17 Size : 8kb Publisher : lee
[Software Engineering] dct-thesis DL : 0: Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
Update : 2025-02-17 Size : 483kb Publisher : student
[Compress-Decompress algrithms] xapp615 DL : 0: IDCT - xlinix design in vhdl-IDCT- xlinix design in vhdl
Update : 2025-02-17 Size : 29kb Publisher : asia
[Special Effects] TDC_3 DL : 0: This is a matrixl 8 * 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realiz-This is a matrixl 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realiz
Update : 2025-02-17 Size : 1kb Publisher : helllano
[mpeg mp3] mpeg2_idct_hw DL : 0: 2-D的DCT/IDCT在軟硬體上的verilog code-dct/idct source code for soc
Update : 2025-02-17 Size : 10.3mb Publisher : 陳伯綸
[Compress-Decompress algrithms] DCTPROGRAM.ZIP DL : 0: it is verilog code for two dimentional dct
Update : 2025-02-17 Size : 18kb Publisher : suhu
[VHDL-FPGA-Verilog] attachments_2010_01_29 DL : 0: dct and idct vhdl code
Update : 2025-02-17 Size : 71kb Publisher : suhu
[VHDL-FPGA-Verilog] DCT_IDCT DL : 0: verilog code for DCT and IDCT (JPEG)
Update : 2025-02-17 Size : 62kb Publisher : Dang Tien Dat
[VHDL-FPGA-Verilog] Axi_mux DL : 0: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Update : 2025-02-17 Size : 41kb Publisher : Paul Stephen

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