Search - ide fpga

[Embeded-SCM Develop] vhdlcodes3

Description: FPGA/CPLD集成开发环境ISE使用详解实例－3-FPGA/CPLD integrated development environment IDE ISE example-3
Platform: | Size: 74752 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcodes4

Description: FPGA/CPLD集成开发环境ISE使用详解实例－4-FPGA/CPLD integrated development environment IDE ISE example-4
Platform: | Size: 149504 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcodes5

Description: FPGA/CPLD集成开发环境ISE使用详解实例－5-FPGA/CPLD integrated development environment IDE ISE example-5
Platform: | Size: 152576 | Author: 邓志斌 | Hits:

[Embeded-SCM Develop] vhdlcdes6

Description: FPGA/CPLD集成开发环境ISE使用详解实例－6-FPGA/CPLD integrated development environment IDE ISE example-6
Platform: | Size: 19456 | Author: 邓志斌 | Hits:

[Other Embeded program] Development_Guide_of_socFPG

Description: socFPGA开发简明教程教程以非常详细的实例来让初学者了解基于QuartusII和NiosII IDE的FPGA/SOPC开发基本流程。-Concise Guide socFPGA developed a very detailed tutorial with examples to get beginners to understand QuartusII and NiosII IDE based on the FPGA/SOPC development of the basic processes.
Platform: | Size: 1629184 | Author: tian | Hits:

[VHDL-FPGA-Verilog] xst3_IDE

Description: Access IDE harddisk by Xilinx FPGA Support PIO2-err
Platform: | Size: 33792 | Author: ronsullivan | Hits:

[ARM-PowerPC-ColdFire-MIPS] SDCard_test

Description: SD卡的SPI驱动程序，已在Nios2 IDE 中调试成功-SD card SPI driver, has been successful Nios2 IDE in debug
Platform: | Size: 24576 | Author: jzt | Hits:

[VHDL-FPGA-Verilog] xilinxIDE

Description: xilinx fpga 下的IDE控制器原代码,贡献一起学习-xilinx fpga controller under the IDE source code and contribute to study together
Platform: | Size: 31744 | Author: fangming | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] ActelFPGA_IDE_ApplicationNote

Description: IDE 硬盘具有容量大、速度快、成本低的特点，因此被广泛应用于各种工业控制、消费、通信、安防等场合，而 IDE 控制器解决方案成为了大家所关注的焦点，由于基于 MCU的 IDE 控制器速度低、成本高、不够灵活等缺点使得应用越来越少，更多的用户倾向于使用 FPGA 来提供更完美的解决方案。本方案采用 Actel Flash 架构的 FPGA 来实现 IDE 的控制器，具有单芯片、高性能、低成本等特点，满足客户各种应用需求，该方案已经被多家公司采纳。 -IDE disk with large capacity, speedy, low cost, thus has been widely used in various industrial control, consumption, Communication, security and so on, and IDE controller solutions for all the focus of attention, because of MCU based on the IDE Low speed controller, the high cost and shortcomings, such as flexible enough to make fewer application more users tend to use the FPGA To provide more perfect solution. The scheme adopts Actel Flash framework to realize the FPGA IDE controller Have single chip, high performance and low cost, etc. To meet customer demand, the solution of application has been adopted by many companies.
Platform: | Size: 296960 | Author: zxx359654879 | Hits:

[Communication-Mobile] NiosII-LED-Demo

Description: 这是 Quartues II 的 FPGA SOPC NIOS_II IDE的设历程，对于初学者肯定有很大的帮助-This is a Quartues II of the FPGA SOPC NIOS_II IDE to set the course for beginners will definitely be very helpful
Platform: | Size: 317440 | Author: hanbin | Hits:

[VHDL-FPGA-Verilog] Nios_II_SPI

Description: 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
Platform: | Size: 16035840 | Author: huangshengqun | Hits:

[VHDL-FPGA-Verilog] Nios_II_uCOS

Description: 本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
Platform: | Size: 13812736 | Author: huangshengqun | Hits:

[Video Capture] video_board_schemtic1

Description: this the schemtic for hooking up a video encoding chip (SAA7121H) to a IDE connector so it can connect to a DE1 FPGA board or any other you fancy-this is the schemtic for hooking up a video encoding chip (SAA7121H) to a IDE connector so it can connect to a DE1 FPGA board or any other you fancy
Platform: | Size: 27648 | Author: ghost | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Platform: | Size: 3072 | Author: 尹长生 | Hits:

[VHDL-FPGA-Verilog] Verilog000

Description: FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。
Platform: | Size: 22794240 | Author: onejacky | Hits:

[VHDL-FPGA-Verilog] Libero8.3

Description: 介绍了 Actel FPGA 的集成开发环境 IDE 的使用，从软件的安装和设置，以及通过一个简单的例子说明如何使用 IDE中集成的第三方软件，如：Synplify、ModelSim等，可以帮助读者快速入门，缩短开发时间。-Actel FPGA introduced the use of IDE integrated development environment, from software installation and setup, as well as through a simple example of how to use the IDE, integrated third-party software, such as: Synplify, ModelSim, etc., can help readers get started quickly, shortening development time.
Platform: | Size: 2623488 | Author: anranxjk | Hits:

[VHDL-FPGA-Verilog] SHA256_SYSTEM

Description: 利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。(The hardware (programmable logic device FPGA) is used to implement the cryptographic algorithm SHA256, and the soft core NIOSii is embedded in the FPGA, and the software is programmed on the NIOSii. The hardware EDA tool is the Quartus II of ALTERA, and the software IDE is eclipse (embedded in Quartua).)
Platform: | Size: 4413440 | Author: 风@筝 | Hits:

[VHDL-FPGA-Verilog] eeprom_test_Verilog

Description: eeprom工程，实现了基本的读写，供参考。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置和逻辑可控制。(EEPROM project, the realization of the basic reading and writing for reference. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify pin configuration and logic control according to its own hardware.)
Platform: | Size: 159744 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] uart_test_Verilog

Description: 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configuration according to its own hardware.)
Platform: | Size: 128000 | Author: shaoyang_v | Hits:

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