Search - ieee 1364

[Other resource] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE

Description: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Platform: | Size: 380828 | Author: 王刚 | Hits:

[Other resource] ieee-std-1364

Description: 做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
Platform: | Size: 1429478 | Author: 周贤 | Hits:

[Other Embeded program] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE

Description: IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar-IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Platform: | Size: 380928 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] ieee-std-1364

Description: 做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
Platform: | Size: 1429504 | Author: 周贤 | Hits:

[Other] iir_par_code

Description: IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
Platform: | Size: 1024 | Author: 无名 | Hits:

[Other] Kluwer.The.Verilog.Hardware.Description.Language.5

Description: Verilog硬件描述语言，第五版 Thomas&Moorby等著。权威的Verilog介绍，包含IEEE-1364 2001 标准 -The Verilog® Hardware Description Language, Fifth Edition. By Thomas&Moorby
Platform: | Size: 7194624 | Author: Jasper Hu | Hits:

[Other] SamilPalnitkar

Description: Verilog HDL A Guide to Digital Design and Synthesis, Second edition IEEE 1364-2001 compliant by Samir Palnitkar. This book will definitely going to be very useful for the beginners as the contents of it are well explained with proper examples and illustrations. The author starts the language from very scratch to professional level.
Platform: | Size: 1723392 | Author: rksant | Hits:

[Software Engineering] IEEE_Verilog_2001

Description: Verilog 2001 编程规范中文版，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
Platform: | Size: 2236416 | Author: 徐杰猛 | Hits:

[VHDL-FPGA-Verilog] PalnitkarVerilogHDL

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: Amir | Hits:

[Other] Verilog_HDL

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: lucer_29a | Hits:

[Embeded-SCM Develop] iverilog-0.9.2

Description: iverilog是verilog仿真综合工具，能够将verilog源代码编译为不同的目标文件-Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format
Platform: | Size: 1477632 | Author: fanyuchuan | Hits:

[VHDL-FPGA-Verilog] Introduction-to-Verilog

Description: Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, -Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, Verilog 1364
Platform: | Size: 191488 | Author: zhujizhen | Hits:

[File Format] verilog-ieee.pdf.tar

Description: IEEE 2001 verilog 标准 ,详细讲述了业内公认的 VERILOG 标准 ,-The Verilog¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.
Platform: | Size: 2200576 | Author: adam | Hits:

[Software Engineering] Verilog-IEEE-Std(1364-2005)

Description: Verilog IEEE Std(1364-2005) 标准,硬件开发必备手册-Verilog IEEE Std (1364-2005) standards, hardware development of the necessary manual
Platform: | Size: 3174400 | Author: panqihe | Hits:

[Other] 2005-Verilog-IEEE-Std(1364-2005)

Description: IEEE Standard for Verilog Hardware Description Language 1364-2005 verilog2005版本的标准-IEEE Standard for Verilog Hardware Description Language 1364-2005
Platform: | Size: 3185664 | Author: 赵先生 | Hits:

[VHDL-FPGA-Verilog] Prentice---Verilog.HDL_A.Guide.to.Digital.Design.

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.-Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: bom | Hits:

[Other] Verilog-

Description: Verilog hardware description language-IEEE Std 1364-2001 Standard Verilog hardware description language
Platform: | Size: 2174976 | Author: george | Hits:

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