Search - image compression in vhdl

[Graph program] jpeg_src

Description: 是jpeg标准下图象压缩的vhdl实现工程,包括core文件,测试文件,工程文件-image compression vhdl realization project under standard jpeg.core files, test files and project files are included.
Platform: | Size: 1569792 | Author: 石伟 | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[VHDL-FPGA-Verilog] shipingkonzhi

Description: 用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,
Platform: | Size: 431104 | Author: 张龙 | Hits:

[Multimedia program] video_compression_systems.tar

Description: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Platform: | Size: 186368 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: HDTV视频内容创作的繁荣以及在带宽受限的广播信道环境中传送这些视频内容的方法，不断催生新的视频压缩标准和相关视频图像处理设备。-HDTV video content creation and prosperity as well as bandwidth-constrained environment of the broadcasting channel to send video content of these methods, birth of a new video compression standards and associated video image processing equipment.
Platform: | Size: 59392 | Author: chenqunqin | Hits:

[Wavelet] compressVLSI

Description: 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-High-speed image compression encoder the structural design of VLSI Research. Kdh quite the level of doctoral dissertation. Which describes in detail how to design the structure of wavelet transform VLSI. Verilog hdl design and structure of the assessment
Platform: | Size: 1733632 | Author: 黄辉 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG标准下图象压缩的VHDL实现工程，包含文档，原代码及测试代码-JPEG image compression standard of VHDL realization of the project, including documentation, source code and test code
Platform: | Size: 1474560 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] fpgajpeg

Description: 基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
Platform: | Size: 103424 | Author: 倪德 | Hits:

[VHDL-FPGA-Verilog] JPEGvhdl

Description: JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
Platform: | Size: 260096 | Author: 姚大雷 | Hits:

[Picture Viewer] jpeg_rgb

Description: 这是JPEG图像压缩的RGB转换的源代码，其中还包括了它的仿真测试代码，希望能帮助到大家。-This is the JPEG image compression of RGB conversion source code, including its simulation test code, hoping to help you.
Platform: | Size: 3072 | Author: mary | Hits:

[VHDL-FPGA-Verilog] fpga_jpeg

Description: 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Platform: | Size: 103424 | Author: 沧海一笑 | Hits:

[VHDL-FPGA-Verilog] FPGA_image

Description: fpga实现图像处理，JPEG标准下图象压缩，VHDL语言编程。-fpga implementation image processing, JPEG image compression under the standard, VHDL language programming.
Platform: | Size: 295936 | Author: xiangchuiyi | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] JPEG

Description: 本文首先介绍了静态图像压缩（JPEG）编码算法的基本原理、压缩的实现过程及其重要过程的离散余弦变换（DCT）算法的实现原理及软件实现的例程，其次着重介绍了压缩过程中的DCT、量化和编码三个重要步骤的实现原理。-This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation process and its important discrete cosine transform (DCT) Algorithm theory and software implementation of the routines, followed by highlights of the compression process DCT, quantization and encoding steps in the realization of three important principles.
Platform: | Size: 41984 | Author: xuai | Hits:

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