Search - image enhancement verilog

[VHDL-FPGA-Verilog] image_enhacement_fpga

Description: Image Enhancement algorithms implemented on FPGA in the literature. Papers are added.
Platform: | Size: 3221504 | Author: hazan | Hits:

[VHDL-FPGA-Verilog] histogram-equalization-verilog

Description: 直方图均衡的Verilog实现从Matlab读出图像为image.txt文件，经过Modelsim读入TXT文件进行直方图均衡处理，将输出结果再读出为image_he.txt文件，然后在Matlab观察直方图均衡增强效果。-The histogram equalization Verilog read from Matlab the image image.txt file after the Modelsim read into the TXT file, histogram equalization processing, and output the results read out for image_he.txt file, then the histogram equalization enhancement observed in Matlab.
Platform: | Size: 2048 | Author: 杨光 | Hits:

[Software Engineering] april2010_1

Description: 基于FPGA的方向滤波指纹图像增强算法实现，本文利用FPGA具有丰富寄存器资源、可满足高速系统设计等特点，设计了一种基于FPGA纯硬件方式实现方向滤波的指纹图像增强算法。设计采用寄存器传输级（RTL）硬件描述语言（Verilog HDL），利用时分复用和流水线处理等技术，完成了方向滤波指纹图像增强算法在FPGA上的实现。-Directional filtering fingerprint image enhancement algorithm based on FPGA using the FPGA has a rich register resources to meet the high-speed system design, design direction filtering a pure hardware FPGA-based fingerprint image enhancement algorithm. The design uses a register-transfer level (RTL) hardware description language (Verilog HDL), time division multiplexing and pipelining technology to complete the realization of the direction of filtering fingerprint image enhancement algorithm on the FPGA.
Platform: | Size: 928768 | Author: kudding | Hits:

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[VHDL-FPGA-Verilog] image_enhacement_fpga

[VHDL-FPGA-Verilog] histogram-equalization-verilog

[Software Engineering] april2010_1

[VHDL-FPGA-Verilog] major1_contrast

[VHDL-FPGA-Verilog] major_threshold

[VHDL-FPGA-Verilog] major_brightness

[VHDL-FPGA-Verilog] major1

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