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Description: This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise.
The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
You should run "Simulation.m" function that include all modules.
Platform: |
Size: 10240 |
Author: 李南 |
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Description: Convolutional Interleaver Encoder-convolutional Interleaver Encoder
Platform: |
Size: 1024 |
Author: 孙晓伟 |
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Description: This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
You should run "Simulation.m" function that include all modules-This packet is a IS-95 baseband simulation for a channel data rate of 9.6 KBps. The simulati on is written for static channel and AWGN noise. The packet include : 1) Packet Builder (Viterbi Encoding. Interleaver. PN generation) 2) Modulator (RRC filter) 3) Dem odulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterl eaver. Viterbi Decoder). You should run "Simulation. m "function that include all modules
Platform: |
Size: 10240 |
Author: lisi |
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Description: interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器,
包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料
-interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials are intertwined
Platform: |
Size: 360448 |
Author: 陈朋 |
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Description: maatlab OFDM交织程序欢迎大家指教-maatlab OFDM-cutting procedures to welcome you enlighten
Platform: |
Size: 1024 |
Author: 往昔 |
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Description: 该程序仿真CDMA接收机的功能，包括解扩，解交织，信道编码(卷积码)，解码，信源编码(CRC)解码5个功能模块，生成用于数字基带传输的信号序列。
仿真CDMA发射机的功能，包括随机序列的产生，信源编码尾比特添加, 信道编码(卷积编码)，分组交织和扩频调制6个功能模块，生成用于数字基带，传输的信号序列，输出还包括用于解调所需要的信源编码尾比特值add_bits，交织器的尾比特值i_add_bits-CDMA receiver functions, including despreading, Xie intertwined, channel coding (convolutional codes), decoded, the source code (CRC) decoder five functional modules, production figures for the base band signal transmission sequence. Simulation CDMA transmitter functions, including random sequence generation, the source coding bit late add, Channel Coding (coding), a spread-spectrum modulation intertwined and six functional modules, production figures for the base-band, The transmission signal sequence, and the output is also included for the modems needed source coding bit value add_bits tail, interleaver value of the last bit i_add_bits
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Size: 3072 |
Author: 刘洪 |
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Description: interleaver design for coding
Platform: |
Size: 1024 |
Author: julia |
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Description: 该程序描述的是数字电视地面广播中卷积交织部分.因为是卷积交织所以最后结果中出现为的数值表示该值是前一包缓冲数据的数.但针对第一包数据做卷积交织时,这些零位置上最后确实自动补零.-The procedure is described in digital TV terrestrial broadcasting in parts of Convolutional Interleaver. Convolutional Interleaver because it is so final results for the numerical value is that the previous data on the number of packet buffer. But for the first packet data do Convolutional Interleaver These zero position is indeed the last automatic zero.
Platform: |
Size: 2048 |
Author: Sue |
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Description: 基于FPGA的Turbo码交织器的设计与实现
比较实用-FPGA-Based Turbo Code Interleaver Design and Implementation of a more practical
Platform: |
Size: 371712 |
Author: mediative |
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Description: turbo码中各种交织器的设计，可以据此改编，设计出适合系统需要的交织器-a variety of turbo code interleaver design can be adapted accordingly, need to design a suitable system of interleaver
Platform: |
Size: 2048 |
Author: wxp |
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Description: 用C语言编写的交织器，包括3GPP交织器，随机交织器，螺旋交织器，对角交织器，块交织，循环交织器等-Using C language interleaver, including the 3GPP interleaver, random interleaver, interleaver spiral, diagonal interleaver, block cutting, cutting cycle, etc.
Platform: |
Size: 6144 |
Author: 王雨 |
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Description: VHDL编写的基于FPGA的4-8交织器代码，有需要的下来-4-8 prepared VHDL code interleaver
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Size: 1024 |
Author: cab |
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Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: |
Size: 2048 |
Author: tomsontiger |
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Description: 这是一个用VHDL编写的交织器程序,使用交织器能够使干扰由突发变成随机化-This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
Platform: |
Size: 1024 |
Author: chenxiaoming |
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Description: WLAN FEC interleaver for Encoder
i=(Ncbps/16)(kmod 16) + floor(k/16)
for 802.11a Test simualtion-WLAN FEC interleaver for Encoder
i=(Ncbps/16)(kmod 16)+ floor(k/16)
for 802.11a Test simualtion
Platform: |
Size: 1024 |
Author: Kim Myung Ick |
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Description: Interleaver is used in the physical layer of a wireless communication to combat the burst errors that are inherent in the wireless communication systems. WiMAX does tow level of interleaving.
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Size: 1024 |
Author: muruga |
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Description: 自己做的交织器，里面包含了交织器的源程序，和交织器的仿真电路文件等等。。。调试后，实现结果正确-Do their own interleaver, which contains the source code interleaver and interleaver circuit simulation files and so on. . . After commissioning, to achieve the right results
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Size: 25600 |
Author: luyan |
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Description: s-交织器，能对序列进行交织，保证交织序列交织分散-s-interleaver, can be interleaved sequence to ensure the cutting sequence spread intertwined
Platform: |
Size: 1024 |
Author: 刘阔 |
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Description: interleaver for wi max phy
Platform: |
Size: 1024 |
Author: beshoy |
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Description: vhdl code for interleaver
Platform: |
Size: 1024 |
Author: aruna |
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