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[VHDL-FPGA-Verilog] interleave

Description: 数据交织器 verilog HDL源文件-Data interleaver verilog HDL source file
Platform: | Size: 100352 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] 4_31

Description: 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
Platform: | Size: 834560 | Author: 谢建伟 | Hits:

[VHDL-FPGA-Verilog] interleaver-vhdl

Description: VHDL编写的基于FPGA的4-8交织器代码，有需要的下来-4-8 prepared VHDL code interleaver
Platform: | Size: 1024 | Author: cab | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
Platform: | Size: 27648 | Author: 尚龙 | Hits:

[Other] FPGA_interleaver

Description: 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
Platform: | Size: 120832 | Author: xx | Hits:

[VHDL-FPGA-Verilog] jiaozhiqi

Description: 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
Platform: | Size: 765952 | Author: 郑国 | Hits:

[VHDL-FPGA-Verilog] interweave_1

Description: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
Platform: | Size: 36864 | Author: 李修函 | Hits:

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