Search - interleaver VHDL code

Search - interleaver VHDL code - List

[Embeded-SCM Develop] interleave DL : 0: 块交织的verilog代码--Verilog code for interleave.
Update : 2025-02-17 Size : 1kb Publisher :
[VHDL-FPGA-Verilog] suij DL : 0: 硬件编程实现伪随机交织器和随机交织器，应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
Update : 2025-02-17 Size : 2kb Publisher : 孟旭
[GDI-Bitmap] verilog_interleave1 DL : 0: 里面是5个关于交织器的源代码，有兴趣的可以下来学习一下-There is a 5 on the interleaver of the source code, are interested in learning what can be down
Update : 2025-02-17 Size : 11kb Publisher : 吴雨彤
[VHDL-FPGA-Verilog] veriloginterleave2 DL : 0: 交织器的在5个源代码，:-) 对学习交织器真的很有用的啊 -Interleaver in 5 source code, :-) learning interleaver ah really useful
Update : 2025-02-17 Size : 11kb Publisher : 吴雨彤
[VHDL-FPGA-Verilog] interleave DL : 0: 数据交织器 verilog HDL源文件-Data interleaver verilog HDL source file
Update : 2025-02-17 Size : 98kb Publisher : 长空
[VHDL-FPGA-Verilog] 4_31 DL : 0: 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
Update : 2025-02-17 Size : 815kb Publisher : 谢建伟
[VHDL-FPGA-Verilog] interleaver-vhdl DL : 0: VHDL编写的基于FPGA的4-8交织器代码，有需要的下来-4-8 prepared VHDL code interleaver
Update : 2025-02-17 Size : 1kb Publisher : cab
[Other] interleaver DL : 0: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Update : 2025-02-17 Size : 2kb Publisher : tomsontiger
[VHDL-FPGA-Verilog] interleaver DL : 0: 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
Update : 2025-02-17 Size : 27kb Publisher : 尚龙
[Communication] Turbo DL : 1: 利用3GPP交织器和LTE交织器完成turbo码的仿真并做比较，不同解码算法的比较-Using 3GPP Interleaver and complete LTE interleaver turbo code simulation and comparison, a comparison of different decoding algorithms
Update : 2025-02-17 Size : 110kb Publisher : 老五
[Program doc] DVB DL : 0: DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
Update : 2025-02-17 Size : 692kb Publisher : 程钢
[Other] FPGA_interleaver DL : 0: 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
Update : 2025-02-17 Size : 118kb Publisher : xx
[VHDL-FPGA-Verilog] jiaozhiqi DL : 0: 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
Update : 2025-02-17 Size : 748kb Publisher : 郑国
[VHDL-FPGA-Verilog] interweave_1 DL : 0: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
Update : 2025-02-17 Size : 36kb Publisher : 李修函
[VHDL-FPGA-Verilog] interleaver DL : 0: vhdl code for interleaver
Update : 2025-02-17 Size : 1kb Publisher : aruna
[VHDL-FPGA-Verilog] INTERLEAVER DL : 0: 1/3,k=9的卷积码VHDL实现,在xilinx ise上仿真成功。-1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
Update : 2025-02-17 Size : 1kb Publisher : 杨胜丰
[VHDL-FPGA-Verilog] 15Turbo DL : 0: urbo码是1993年法国人Berrou提出的一种新型编码方法。它巧妙的将卷积码和随机交织器结合在一起；同时，采用软输出迭代译码来逼近最大似然译码-urbo code is 1993 French Berrou proposed a new encoding method. It is clever to convolutional codes and random interleaver together the same time, the use of soft-output iterative decoding to approximate the maximum likelihood decoding
Update : 2025-02-17 Size : 61kb Publisher : wangzhi
[Modem program] interleaver DL : 0: In this case is a interleaving algorithm code for deinterleaving the code, using VHDL language. This code provide the method of interleaving of the convolutioned code
Update : 2025-02-17 Size : 6kb Publisher : kimdaeyoung
[Program doc] interleaver-vhdl-code DL : 0: lte turbo interleaver
Update : 2025-02-17 Size : 140kb Publisher : sampath
[Program doc] VHDL-implementation DL : 0: document discribe the way how to implemete an interleaver using VHDL code
Update : 2025-02-17 Size : 6.73mb Publisher : essedik