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[
VHDL-FPGA-Verilog
]
ISP1362
Description:
Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
Platform:
|
Size:
18432
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Author:
zhyy
|
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