Search - jpeg compression in verilog

Search - jpeg compression in verilog - List

[VHDL-FPGA-Verilog] verilog_jpeg DL : 0: 用verilog 描写应用于数字图像压缩系统--jpeg 有测试文档-using Verilog description applied to digital image compression system-- a test jpeg files
Update : 2025-02-17 Size : 9kb Publisher : 周信均
[Compress-Decompress algrithms] 601792346200732319490634862 DL : 0: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Update : 2025-02-17 Size : 5kb Publisher : wuguanying
[VHDL-FPGA-Verilog] jpeg DL : 0: JPEG标准下图象压缩的VHDL实现工程，包含文档，原代码及测试代码-JPEG image compression standard of VHDL realization of the project, including documentation, source code and test code
Update : 2025-02-17 Size : 1.41mb Publisher : 王刚
[VHDL-FPGA-Verilog] huffman DL : 0: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 10kb Publisher : caesar
[VHDL-FPGA-Verilog] quant DL : 0: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 14kb Publisher : caesar
[VHDL-FPGA-Verilog] rle DL : 0: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 4kb Publisher : caesar
[VHDL-FPGA-Verilog] zigzag_decode DL : 0: 用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
Update : 2025-02-17 Size : 3kb Publisher : caesar
[VHDL-FPGA-Verilog] JPEGvhdl DL : 0: JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
Update : 2025-02-17 Size : 254kb Publisher : 姚大雷
[VHDL-FPGA-Verilog] fpga_jpeg DL : 0: 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Update : 2025-02-17 Size : 101kb Publisher : 沧海一笑
[source in ebook] 63535312DCTofJPEG DL : 0: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Update : 2025-02-17 Size : 2kb Publisher : jiang
[source in ebook] Chapter1-5 DL : 0: 第一章到第五章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update : 2025-02-17 Size : 1.51mb Publisher : xiao
[VHDL-FPGA-Verilog] Chapter6-9 DL : 0: 第六章到第九章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update : 2025-02-17 Size : 5.99mb Publisher : xiao
[VHDL-FPGA-Verilog] Chapter10 DL : 0: 第十章的代码。本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Update : 2025-02-17 Size : 6.55mb Publisher : xiao
[VHDL-FPGA-Verilog] Chapter11-13 DL : 0: 第十一章到第十三章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Update : 2025-02-17 Size : 4.85mb Publisher : xiao
[VHDL-FPGA-Verilog] JPEG DL : 0: 用Verilog描写应用于数字图像压缩系统--JPEG有测试文档-With Verilog description of the system used in digital image compression- JPEG with test documentation
Update : 2025-02-17 Size : 10kb Publisher : changliang
[Compress-Decompress algrithms] dct2d DL : 0: this program is written in verilog compute the dct transform of an image used for jpeg and other image compression methods-this program is written in verilog compute the dct transform of an image used for jpeg and other image compression methods
Update : 2025-02-17 Size : 4kb Publisher : mary