Search - jpeg in vhdl

[Graph program] jpeg_src

Description: 是jpeg标准下图象压缩的vhdl实现工程,包括core文件,测试文件,工程文件-image compression vhdl realization project under standard jpeg.core files, test files and project files are included.
Platform: | Size: 1569792 | Author: 石伟 | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[VHDL-FPGA-Verilog] jpeg_vhdl_src

Description: JPEG的硬體設計採用的是VHDL設計,有源碼-JPEG hardware design using VHDL design source code
Platform: | Size: 288768 | Author: 黃彥華 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG标准下图象压缩的VHDL实现工程，包含文档，原代码及测试代码-JPEG image compression standard of VHDL realization of the project, including documentation, source code and test code
Platform: | Size: 1474560 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] quant

Description: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 14336 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] rle

Description: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 4096 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] JPEGvhdl

Description: JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
Platform: | Size: 260096 | Author: 姚大雷 | Hits:

[Picture Viewer] JPEGactFPGA

Description: 利用FPGA实现JPEG算法的研究与实现，研究生的论文，很有参考价值-JPEG algorithm using FPGA realization of Research and Implementation of, post-graduate thesis, a good reference
Platform: | Size: 2592768 | Author: 刘小春 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG(Joint Photographic Expert Group,联合摄影专家组)编码的数据执行解压缩的各项功能.JPEG的VHDL实现代码-JPEG (Joint Photographic Expert Group, Joint Photographic Experts Group) encoding of data to implement the various functions of decompression. JPEG realization of VHDL code
Platform: | Size: 3241984 | Author: 陈 | Hits:

[Picture Viewer] jpeg_rgb

Description: 这是JPEG图像压缩的RGB转换的源代码，其中还包括了它的仿真测试代码，希望能帮助到大家。-This is the JPEG image compression of RGB conversion source code, including its simulation test code, hoping to help you.
Platform: | Size: 3072 | Author: mary | Hits:

[mpeg mp3] jpeg.tar

Description: jpeg硬件压缩代码，对学习jpeg压缩的同学非常有用-hardware jpeg compression code, the Student Study jpeg compression is very useful
Platform: | Size: 1869824 | Author: ma | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

[VHDL-FPGA-Verilog] fpga_jpeg

Description: 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Platform: | Size: 103424 | Author: 沧海一笑 | Hits:

[VHDL-FPGA-Verilog] FPGA_image

Description: fpga实现图像处理，JPEG标准下图象压缩，VHDL语言编程。-fpga implementation image processing, JPEG image compression under the standard, VHDL language programming.
Platform: | Size: 295936 | Author: xiangchuiyi | Hits:

[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] JPEG

Description: 本文首先介绍了静态图像压缩（JPEG）编码算法的基本原理、压缩的实现过程及其重要过程的离散余弦变换（DCT）算法的实现原理及软件实现的例程，其次着重介绍了压缩过程中的DCT、量化和编码三个重要步骤的实现原理。-This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation process and its important discrete cosine transform (DCT) Algorithm theory and software implementation of the routines, followed by highlights of the compression process DCT, quantization and encoding steps in the realization of three important principles.
Platform: | Size: 41984 | Author: xuai | Hits:

[VHDL-FPGA-Verilog] VERILOG-jpeg

Description: 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
Platform: | Size: 103424 | Author: ken | Hits:

[Software Engineering] mkjpeg_latest

Description: jpeg encoder vhdl source code
Platform: | Size: 2244608 | Author: ZES | Hits:

[Compress-Decompress algrithms] JPEG-LS

Description: 基于改进JPEG-LS算法的遥感图像近无损压缩专利，由航天五院508所申报，很详细的介绍了算法和fpga的实现-Improved JPEG-LS algorithm near lossless compression patent, the space the five branches of 508 reporting, a detailed explanation of the algorithm and implementation fpga
Platform: | Size: 673792 | Author: 小化 | Hits:

« 12 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Graph program] jpeg_src

[Compress-Decompress algrithms] 601792346200732319490634862

[VHDL-FPGA-Verilog] jpeg_vhdl_src

[VHDL-FPGA-Verilog] jpeg

[VHDL-FPGA-Verilog] quant

[VHDL-FPGA-Verilog] rle

[VHDL-FPGA-Verilog] JPEGvhdl

[Picture Viewer] JPEGactFPGA

[VHDL-FPGA-Verilog] jpeg

[Picture Viewer] jpeg_rgb

[mpeg mp3] jpeg.tar

[VHDL-FPGA-Verilog] oc_mkjpeg

[VHDL-FPGA-Verilog] fpga_jpeg

[VHDL-FPGA-Verilog] FPGA_image

[source in ebook] 63535312DCTofJPEG

[source in ebook] Chapter1-5

[VHDL-FPGA-Verilog] JPEG

[VHDL-FPGA-Verilog] VERILOG-jpeg

[Software Engineering] mkjpeg_latest

[Compress-Decompress algrithms] JPEG-LS

CodeBus www.codebus.net