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[VHDL-FPGA-Verilogverilog_usbblaster

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine
Platform: | Size: 1570816 | Author: 一王 | Hits:

[VHDL-FPGA-VerilogUSB_jtag

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
Platform: | Size: 1571840 | Author: 霍飘摇 | Hits:

[Otherc73a2ceb-09a5-4366-83ea-78b08c6200eb

Description: jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
Platform: | Size: 2048 | Author: 张涛 | Hits:

[Other systemsjtag_ver1_5

Description: C++ classes for JTAG over LPT port. Allows to execute the following commands: - RESET - move TAP-controller from any state to RESET - IDLE - move TAP-controller from RESET state to Run/Idle state - IRSCAN - scan-in specified JTAG-command - DRSCAN - scan-in specified JTAG-data-C++ classes for JTAG over LPT port. Allows to execute the following commands: - RESET - move TAP-controller from any state to RESET - IDLE - move TAP-controller from RESET state to Run/Idle state - IRSCAN - scan-in specified JTAG-command - DRSCAN - scan-in specified JTAG-data
Platform: | Size: 7168 | Author: Roman | Hits:

[VHDL-FPGA-Verilogjtag fsm

Description: jtag接口的状态机实现,李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)
Platform: | Size: 2048 | Author: xilingsnow | Hits:

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