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[Embeded-SCM Develop] HighResTimer

Description: * 一、功能: Timestamp驱动演示代码. * 二、该源码需要硬件开发板的支持,因为ISS对Timestamp定时器的模拟还不够精确 * 如果将该源码运行于ISS模式下,将得不到精确的结果 * 三、运行前提: * 1. 选择包含JTAG_UART和定时器的NiosII系统(ptf文件) * 其中的定时器要求: * (1) 具备可写的period寄存器 * (2) 具备可读的snapshot寄存器 * 2. 在系统库属性中完成下面的配置: * (1) 将stdout映射到JTAG_UART * (2) 将定时器映射为Timestamp时钟
Platform: | Size: 1149 | Author: 李天 | Hits:

[Other Embeded program] JTAG_UART

Description: JTAG_UART的VERILOG代码
Platform: | Size: 4041 | Author: basketballn@163.com | Hits:

[Embeded-SCM Develop] HighResTimer

Description: * 一、功能: Timestamp驱动演示代码. * 二、该源码需要硬件开发板的支持,因为ISS对Timestamp定时器的模拟还不够精确 * 如果将该源码运行于ISS模式下,将得不到精确的结果 * 三、运行前提: * 1. 选择包含JTAG_UART和定时器的NiosII系统(ptf文件) * 其中的定时器要求: * (1) 具备可写的period寄存器 * (2) 具备可读的snapshot寄存器 * 2. 在系统库属性中完成下面的配置: * (1) 将stdout映射到JTAG_UART * (2) 将定时器映射为Timestamp时钟 -* 1, function: Timestamp-driven presentation code.* Second, the source needs the support of hardware development boards, because ISS on Timestamp timer analog also not precise enough* If the source code running on the ISS model, will not be* Third, accurate results, run the premise:* 1. JTAG_UART choose to include and NiosII system timer (ptf files)* one timer requirements:* (1) can be written in a period register* (2) have readable snapshot register* 2. in the system library properties to complete the following configuration:* (1) stdout is mapped to the JTAG_UART* (2) will be mapped to Timestamp timer clock
Platform: | Size: 1024 | Author: 李天 | Hits:

[VHDL-FPGA-Verilog] jtag_uart

Description: Configuration and usage of Altera s JTAG UART.
Platform: | Size: 5648384 | Author: shahbaz | Hits:

[VHDL-FPGA-Verilog] jtag_uart

Description: 用verilog 语言写的jtag_uart程序用于实现jtag的串口通信-Using verilog language written in jtag_uart procedures used to implement the serial communication jtag
Platform: | Size: 4096 | Author: tianyu | Hits:

[VHDL-FPGA-Verilog] jtag_uart

Description: jtag_uart实现FPGA内部和计算机之间的通信，实时监控方便-jtag_uart achieve FPGA communication between the internal and the computer, real-time monitoring convenience
Platform: | Size: 3365888 | Author: 王晓杰 | Hits:

[VHDL-FPGA-Verilog] jtag_uart

Description: SOPC jtag uart 系统集成编译的IP核-Jtag-uart IP core in SOPC
Platform: | Size: 5120 | Author: zy | Hits:

[VHDL-FPGA-Verilog] jtag_atlantic_terminal

Description: jtag communication between on chip jtag_uart and PC host
Platform: | Size: 20480 | Author: gronkjear | Hits:

[VHDL-FPGA-Verilog] jtag_uart

Description: （2）实验2：JTAG UART通信实验，完整的设计工程文件在jtag_uart文件夹下-(2) Experiment 2: the JTAG UART communication experiment, complete design engineering the file in jtag_uart file folder
Platform: | Size: 13440000 | Author: boyzone | Hits:

[VHDL-FPGA-Verilog] DE2-115_Basic_Computer

Description: BASIC COMPUTER FOR JTAG_UART
Platform: | Size: 693248 | Author: chun354 | Hits:

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