Search - key vhdl

[Other resource] key

Description: 自己用VHDL写的键盘程序，设计了防抖动环节
Platform: | Size: 308173 | Author: xu wen qiang | Hits:

Description: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Platform: | Size: 2048 | Author: 汪汪 | Hits:

[VHDL-FPGA-Verilog] key_scan1

Description: 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
Platform: | Size: 594944 | Author: 大圣 | Hits:

[VHDL-FPGA-Verilog] sdramusevhdl

Description: sdram的vhdl实现本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
Platform: | Size: 84992 | Author: cxr | Hits:

[VHDL-FPGA-Verilog] KEY12

Description: １３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners
Platform: | Size: 1024 | Author: 相耀 | Hits:

[VHDL-FPGA-Verilog] VHDLDPLL

Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
Platform: | Size: 167936 | Author: 李湘鲁 | Hits:

[Embeded-SCM Develop] VHDLRAM

Description: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Platform: | Size: 30720 | Author: 刘浏 | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[assembly language] C51CrossLight

Description: 1.设计一个交通灯控制器。 2.利用学习机上的发光二极管，设定东、南、西、北4个方向，各3个灯（红、黄、绿）。交通灯控制器正常工作时，南北方向红灯亮3秒，黄灯闪2秒，绿灯亮3秒，以此类推。东西方向绿灯亮3秒，黄灯闪2秒，红灯亮3秒，以此类推。 3.设定两个紧急按钮，一个控制南北灯，一个控制东西灯。当按下相应的紧急键时，其控制方向的交通灯亮绿灯，其他方向的交通灯亮红灯，至自控键松开，恢复正常交通控制。 -1. Design of a traffic light controller. 2. Use of learning machine on the LED and set the East, South, West, North 4 direction, the three lights (red, yellow, green). Traffic signal controller normal working hours, the north- and south-bound red light three seconds, two seconds flashing yellow light, green light-three seconds, and so on. East-west direction green three seconds, two seconds flashing yellow light, red light three seconds, and so on. 3. Set two emergency buttons, a north-south control lights, a light control things. When pressing the corresponding key emergency, its control the traffic lights green, the other direction, the traffic lights class. Key to loose control and restore normal traffic control.
Platform: | Size: 10240 | Author: wangpeng | Hits:

[VHDL-FPGA-Verilog] keyboard

Description: 矩阵键盘的vhdl编程,非常的实用,带有去抖动 -Matrix keyboard VHDL programming, very practical, with a to-jitter
Platform: | Size: 297984 | Author: zjc | Hits:

[VHDL-FPGA-Verilog] key

Description: 自己用VHDL写的键盘程序，设计了防抖动环节-Use VHDL to write their own keyboard program designed防抖动links
Platform: | Size: 308224 | Author: xu wen qiang | Hits:

[VHDL-FPGA-Verilog] led_key

Description: FPGA EP2C5Q288C8 KEY操作原码,测试OK 打开即用.-FPGA EP2C5Q288C8 KEY operate the original code, test that is used to open OK.
Platform: | Size: 184320 | Author: kenychen | Hits:

[Windows Develop] key

Description: 密码锁控制器设计一个密码锁，平时处于等待状态。管理员可以设置或更该密码。如果不预置密码，密码缺省为“6666”。用户如果需要开锁，按相应的按键进入输入密码状态，输入4位密码，按下确定键后，若密码正确，锁打开，若密码错误，将提示密码错误，要求重新输入，三次输入都错误，将发出报警信号。报警后，只有管理员作相应的处理才能停止报警。用户输入密码时，若输入错误，在按下确定键之前，可以通过按取消键重新输入。正确开锁后，用户处理完毕后，按下确定键，系统回到等待状态。系统操作过程中，只要密码锁没有打开，如果1 分钟没有对系统操作，系统回到等待状态。 -Password lock controller Designed a password lock, waiting in a normal status. Administrators can set up or the password. If you do not preset password, Default password is "6666." If you need to unlock the user, according to the corresponding status button to enter a password, type 4 Password, press OK, if the password is correct, open the lock, if the wrong password, wrong password will be prompted to request re- New inputs, the importation of all three errors, will issue a warning signal. Alarm, only the administrator can deal with accordingly Stop the alarm. Users to enter a password, if the input error, identified in the press before the key can be canceled by pressing the key re- New input. Unlock right, the user after the treatment, press OK, the system back to waiting status. System Operator As long as there is no open locks, 1 minutes, if not on the system operation, system status back to wait.
Platform: | Size: 1024 | Author: Jane | Hits:

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[Other resource] key

[VHDL-FPGA-Verilog] anjian

[VHDL-FPGA-Verilog] key_scan1

[VHDL-FPGA-Verilog] sdramusevhdl

[VHDL-FPGA-Verilog] KEY12

[VHDL-FPGA-Verilog] VHDLDPLL

[Embeded-SCM Develop] VHDLRAM

[VHDL-FPGA-Verilog] AEScoremodules

[assembly language] C51CrossLight

[VHDL-FPGA-Verilog] keyboard

[VHDL-FPGA-Verilog] key

[VHDL-FPGA-Verilog] led_key

[Windows Develop] key

[VHDL-FPGA-Verilog] key

[VHDL-FPGA-Verilog] vhdl-clock

[Program doc] key_expansion.vhdl

[VHDL-FPGA-Verilog] key

[VHDL-FPGA-Verilog] RC6-block-cipher-using-VHDL

[VHDL-FPGA-Verilog] key

[Communication-Mobile] vhdl按键检测

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