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[Other resourceCPLDoptimize

Description: lattice cpld优化技巧资料,无需密码,下载即用!-lattice cpld optimization techniques, without password, download and use!
Platform: | Size: 297766 | Author: 邓丰涛 | Hits:

[Other resourceDS1002

Description: lattice CPLD 芯片资料,网上不好找,我分享给大家
Platform: | Size: 582110 | Author: wanwenqing | Hits:

[Embeded-SCM Developispvme

Description: 在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。--Generate the VME file required for updating Lattice CPLD in embedded systems.
Platform: | Size: 24759 | Author: 可可 | Hits:

[Embeded-SCM Developispvme_eprom

Description: 在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。基于E2PROM存储- Generate the VME file required for updating Lattice CPLD in embedded systems. It is based on E2PROM.
Platform: | Size: 22516 | Author: 可可 | Hits:

[Embeded-SCM Developsvf2vme

Description: 在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。将一个链上的不同厂家的CPLD产生的SVF文件转换成VME文件--Generate the VME file required for updating Lattice CPLD in embedded systems. It could convert SVF files from different vendor s CPLD to VME file.
Platform: | Size: 33301 | Author: 可可 | Hits:

[ELanguagevoice-cpld

Description: 在CPLD内实现声调和时间的控制,在LATTICE的ISPLEVER6.1下编译通过。可以修改定时时间进行声调的修改
Platform: | Size: 2039 | Author: yangyiping | Hits:

[VHDL-FPGA-Verilog并口的CPLD烧录线,通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)

Description: 并口的CPLD烧录线,通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
Platform: | Size: 2302730 | Author: mikeldm@163.com | Hits:

[Embeded-SCM Developispvme

Description: 在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。--Generate the VME file required for updating Lattice CPLD in embedded systems.
Platform: | Size: 24576 | Author: 可可 | Hits:

[Embeded-SCM Developispvme_eprom

Description: 在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。基于E2PROM存储- Generate the VME file required for updating Lattice CPLD in embedded systems. It is based on E2PROM.
Platform: | Size: 22528 | Author: 可可 | Hits:

[Embeded-SCM Developsvf2vme

Description: 在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。将一个链上的不同厂家的CPLD产生的SVF文件转换成VME文件--Generate the VME file required for updating Lattice CPLD in embedded systems. It could convert SVF files from different vendor s CPLD to VME file.
Platform: | Size: 32768 | Author: 可可 | Hits:

[VHDL-FPGA-Verilog1032yiwei_new

Description: CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code
Platform: | Size: 2048 | Author: 冯达 | Hits:

[VHDL-FPGA-Verilogabel-hdl

Description: lattice的abel-hel开发文档,对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
Platform: | Size: 660480 | Author: evan | Hits:

[OtherCPLDoptimize

Description: lattice cpld优化技巧资料,无需密码,下载即用!-lattice cpld optimization techniques, without password, download and use!
Platform: | Size: 297984 | Author: 邓丰涛 | Hits:

[OtherISPdownload

Description: 各种JTAG:包括ALTERA、ARM、AVR、LATTICE、S52、XILINX。-various JTAG include : Altera, ARM, AVR, LATTICE, S52, XILINX.
Platform: | Size: 182272 | Author: 郭shaojia | Hits:

[BooksFPGAusingall

Description: 针对CPLD的所有应用,使自己花了好长时间才整理出来,分类-CPLD for all applications, so that spent their time before finishing well out of classification
Platform: | Size: 16572416 | Author: 阚建峰 | Hits:

[VHDL-FPGA-Verilogtrafic

Description: CPLD lattice1032 VHDL实现交通灯控制!-CPLD lattice1032 VHDL to achieve control of traffic lights!
Platform: | Size: 144384 | Author: 徐家汇 | Hits:

[Other Embeded programPLDDOWNL

Description: LATTICE公司的CPLD/FPGA的ISP下载电缆PCB设计图。-LATTICE company s CPLD/FPGA s ISP download cable PCB design.
Platform: | Size: 29696 | Author: 吕常智 | Hits:

[ARM-PowerPC-ColdFire-MIPSDS1002

Description: lattice CPLD 芯片资料,网上不好找,我分享给大家
Platform: | Size: 581632 | Author: wanwenqing | Hits:

[ELanguagevoice-cpld

Description: 在CPLD内实现声调和时间的控制,在LATTICE的ISPLEVER6.1下编译通过。可以修改定时时间进行声调的修改-In the CPLD to achieve control of tone and time, in LATTICE under the ISPLEVER6.1 compiled through. Can be modified from time to time time to tone changes
Platform: | Size: 2048 | Author: yangyiping | Hits:

[VHDL-FPGA-Verilogcolorful_signal

Description: 设计并调试好一个VGA彩条信号发生器,并用EDA实验开发系统(拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ,FLEX10K系列的EPF10K10LC84-3 FPGA, ACEX1K系列的 EP1K30 FPGA,Xinlinx 的XC9500系列的XC95108 CPLD,Lattice的ispLSI1000系列的1032E CPLD)进行硬件验证。 设计思路 由系统提供的时钟源引入扫描信号,根据VGA彩色显示器的工作原理,设计出各种颜色编码和行场扫描信号。将并口线从计算机并口与CPLD/FPGA适配板连接好,然后将VGA接口与彩色显示器连接好,彩条信号就可以在显示器中产生,通过按键可以改变产生彩条的方式,共六种彩条信号,两种横彩条,两种竖彩条,两种棋盘格。本实验运用层次化设计出VGA彩条信号发生器,由行场信号模块模块和彩条信号发生模块构成,彩条信号发生器的顶层原理图如图10.7 所示. -err
Platform: | Size: 7168 | Author: lijq | Hits:
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