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[Other resource] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \\ uart source (Verilog) \\ uart source (VHDL) \\ uart16550.tar
Platform: | Size: 295101 | Author: efly | Hits:

[Communication-Mobile] UART_NS16450_BY_Lattice

Description: UART参考设计，功能兼容NS16450, Lattice提供
Platform: | Size: 152238 | Author: harrybird | Hits:

[Other resource] UART 源码 (lattice version)

Description: UART 源码 (lattice version)-UART source (lattice version)
Platform: | Size: 87131 | Author: 了类似 | Hits:

[VHDL-FPGA-Verilog] UART 源码 (lattice version)

Description: UART 源码 (lattice version)-UART source (lattice version)
Platform: | Size: 87040 | Author: 了类似 | Hits:

[VHDL-FPGA-Verilog] uart_vhdl_lattice

Description: UART的rs232通信接口VHDL语言，里面有详细的介绍-UART communication interface rs232 VHDL language, which is described in detail
Platform: | Size: 108544 | Author: 拉拉 | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[MPI] Uart_16550_Verilog_Source

Description: UART_16550_verilogHDL源程序，用在lattice芯片上面运行，保证能用的好资料-UART_16550_verilogHDL source, lattice chip used in the above operation can be used to ensure good information
Platform: | Size: 472064 | Author: 成刚 | Hits:

[Communication-Mobile] UART_NS16450_BY_Lattice

Description: UART参考设计，功能兼容NS16450, Lattice提供-UART reference design, function compatible NS16450, Lattice provides
Platform: | Size: 151552 | Author: harrybird | Hits:

[VHDL-FPGA-Verilog] uart16450

Description: uart 16450合集,xilin altera lattice-collection of uart controller 16450
Platform: | Size: 822272 | Author: jhv | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[source in ebook] UARTWISHBONECompatible---Downloads

Description: 16550 uart code lattice cpld fpga 已经验证-16550 uart ip core
Platform: | Size: 713728 | Author: zjc | Hits:

[Other] UART.ZIP

Description: Lattice用VHDL开发的UART（UARTUniversalAsynchronousReceiverTransmitter）控制器SourceCode -UART Universal Asynchronous Receiver Transmitter SourceCode
Platform: | Size: 388096 | Author: FinFET | Hits:

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