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[Other resource] 标准SDR SDRAM控制器参考设计_verilog_lattice

Description: 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
Platform: | Size: 204299 | Author: 陈旭 | Hits:

[Develop Tools] A Verilog HDL Test Bench Primer

Description: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Platform: | Size: 58083 | Author: 陈正一 | Hits:

[Other resource] verilog_lattice

Description: lattice公司关于verilog语言的培训资料，英文版，非常适用于verilog语言的入门学习-lattice verilog language on the company's training materials, in English, verilog very applicable to the elementary language learning
Platform: | Size: 143617 | Author: 何平 | Hits:

[Other resource] Verilog[lattice]

Description: 这是一有很好价值的verilog教程,本人就因此获意非浅,再次贡献给大家,希望大家有所帮助.
Platform: | Size: 144002 | Author: ixia | Hits:

[VHDL-FPGA-Verilog] 并口的CPLD烧录线，通过跳线支持三大厂家的CPLD/FPGA(Altera,Xilinx,Lattice)

Description: 并口的CPLD烧录线，通过跳线支持三大厂家(Altera,Xilinx,Lattice)的CPLD/FPGA烧录,附有电路图与Verilog HDL文档.使用的芯片为XC9572XL-VQ64
Platform: | Size: 2302730 | Author: mikeldm@163.com | Hits:

[SourceCode] lattice的PLL调用

Description: lattice的PLL模块实现，以及verilog的实现
Platform: | Size: 752 | Author: mojianshusheng | Hits:

[Embeded-SCM Develop] pcit32_lattice

Description: PCI接口的Verilog源代码-PCI connection Verilog source code
Platform: | Size: 397312 | Author: 包盛花 | Hits:

[VHDL-FPGA-Verilog] 标准SDR SDRAM控制器参考设计_verilog_lattice

Description: 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
Platform: | Size: 203776 | Author: 陈旭 | Hits:

[Books] A Verilog HDL Test Bench Primer

Description: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Platform: | Size: 57344 | Author: 陈正一 | Hits:

[Other] verilog_lattice

Description: lattice公司关于verilog语言的培训资料，英文版，非常适用于verilog语言的入门学习-lattice verilog language on the company's training materials, in English, verilog very applicable to the elementary language learning
Platform: | Size: 143360 | Author: 何平 | Hits:

[VHDL-FPGA-Verilog] 9.8_DISP256_GUO

Description: 基于Verilog-HDL的硬件电路的实现 9.8 基于256点阵的汉字显示 　　9.8.1 单个静止汉字显示的设计原理及其仿真实现 　　9.8.2 单个静止汉字显示的硬件实现 　　9.8.3 多个静止汉字显示的设计原理及其硬件实现 　　9.8.4 单个运动汉字显示的设计原理及其硬件实现 　　9.8.5 多个运动汉字显示的设计原理及其硬件实现 -based on Verilog-HDL hardware Circuit of 9.8 based on the lattice of 256 Chinese character display 9.8.1 static single Chinese character display and the design principle Simulation 9.8.2 single Chinese character was geostationary said the number of hardware 9.8.3 static display Chinese characters and hardware design principle to achieve single-9.8.4- Movement of the Chinese character display and hardware design principle to achieve a number of campaigns 9.8.5 Chinese character display and the design principle Hardware Implementation
Platform: | Size: 1024 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[MPI] Uart_16550_Verilog_Source

Description: UART_16550_verilogHDL源程序，用在lattice芯片上面运行，保证能用的好资料-UART_16550_verilogHDL source, lattice chip used in the above operation can be used to ensure good information
Platform: | Size: 472064 | Author: 成刚 | Hits:

[Software Engineering] xp2syscloclkpll

Description: 这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多-Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar
Platform: | Size: 641024 | Author: | Hits:

[VHDL-FPGA-Verilog] Lattice_Verilog

Description: 本文讨论了AR模型及线性预测的原理，在浮点型DSP TMS320C6713B上实现了语音信号线性预测系数(LPC)的提取，并利用LPC系数用Verilog语言实现了AR模型的Lattice结构。-This article discusses the AR model and the principle of linear prediction, in the floating-point DSP TMS320C6713B realize the voice signal on the linear prediction coefficient (LPC) of the extract, and the use of LPC coefficients using Verilog languages realize the AR model Lattice structure.
Platform: | Size: 14336 | Author: 万金油 | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[VHDL-FPGA-Verilog] Verilog[lattice]

Description: 这是一有很好价值的verilog教程,本人就因此获意非浅,再次贡献给大家,希望大家有所帮助.-This is a very good value Verilog tutorial, I am going to be intended to greatly therefore, contribute to the U.S. again, I hope everybody help.
Platform: | Size: 143360 | Author: ixia | Hits:

[VHDL-FPGA-Verilog] VGA_1024×768×85

Description: 用verilog hdl实现的VGA显示彩条信号，其中包括VGA时序、竖彩条、横彩条、棋盘格-Using verilog hdl realize the VGA display color signals, including VGA timing, vertical color, Wang Cai, the checkerboard lattice
Platform: | Size: 450560 | Author: 华磊 | Hits:

[VHDL-FPGA-Verilog] LatticeMico8_v3_0_Verilog

Description: The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.-The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
Platform: | Size: 1155072 | Author: 郭豪偉 | Hits:

[VHDL-FPGA-Verilog] ddr_sdr_latest.tar

Description: 一款DDR400的驱动程序，使用VERILOG语言，在LATTICE—ECP2m的FPGA芯片中实际测试。-A DDR400 driver, using VERILOG language, LATTICE-ECP2m actual test of the FPGA chip.
Platform: | Size: 80896 | Author: liang | Hits:
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