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[matlab07126@52RD_Adaptive

Description: ldpc码的经典程序,针对ldpc自适应调制的码率变换-ldpc code classical procedures against ldpc adaptive modulation rate of transformation
Platform: | Size: 1024 | Author: liu | Hits:

[Software Engineering10vhdlexamples

Description: 10个VHDL程序实例,包括加法器,全加器、函数发生器,选择器等。-10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on.
Platform: | Size: 41984 | Author: petri | Hits:

[Internet-NetworkLDPCcode

Description: LDPC编解码实用程序,主要包含源码以及相应的模块说明文件-LDPC codec utility, the main source-code modules as well as the corresponding documentation
Platform: | Size: 9216 | Author: xurenlong | Hits:

[Communication-MobileDECODE

Description: 低密度奇偶校验码即LDPC码的译码C程序,码长为16位-Low-density parity-check code that is decoding LDPC codes C procedures, code length of 16
Platform: | Size: 1024 | Author: 赵天婵 | Hits:

[Communication-MobileLDPC(VHDL)

Description: 低密度奇偶校验码的VHDL程序,用于LDPC码的硬件实现-LDPC code VHDL program for the LDPC code of hardware implementation
Platform: | Size: 2048 | Author: 赵天婵 | Hits:

[VHDL-FPGA-Verilogldpc_decoder_802_3an

Description: 802.3an ldpc码编码、译码设计,使用VERILOG hdl语言编写,包括测试代码,-802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,
Platform: | Size: 788480 | Author: 聂样 | Hits:

[Communication-MobileLDPCdiedai

Description: 一种低复杂度的LDPC码迭代译码算法,希望大家喜欢-A Low-Complexity Iterative Decoding Algorithm for LDPC code, I hope you like
Platform: | Size: 191488 | Author: 张治邦 | Hits:

[Streaming Mpeg4ldpc_encoder_802_3an.v

Description: LDPC 编码的Verilog源代码,我没有验证,不知道效果如何,与大家分享,供大家参考。-LDPC-coded Verilog source code, I did not verify, I do not know how to share with you, for your reference.
Platform: | Size: 622592 | Author: peter | Hits:

[VHDL-FPGA-VerilogLDPC_Behavioral_VHDL

Description: 用VHDL语言编写的LDPC码硬件实现语言,相对于verilog的,比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
Platform: | Size: 2048 | Author: 王明 | Hits:

[VHDL-FPGA-VerilogbitNode_Behaviora_VHDL

Description: LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
Platform: | Size: 1024 | Author: 王明 | Hits:

[Communication-Mobileldpc

Description: 最近在做毕设,ldpc码的编解码实现,这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
Platform: | Size: 9216 | Author: fly | Hits:

[matlabLDPCBSN

Description: LDPC码既低密度奇偶校验码(Low Density Parity Check Code,LDPC),它由Robert G.Gallager博士于1963年提出的一类具有稀疏校验矩阵的线性分组码,不仅有逼近Shannon限的良好性能,而且译码复杂度较低, 结构灵活,是近年信道编码领域的研究热点,目前已广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域。LDPC码已成为第四代通信系统(4G) -LDPC codes BER simulation under AWGN channel. MacKay-Neal based LDPC matrix. Message encoding uses sparse LU decomposition. There are 4 choices of decoder: hard-decision/bit-flip decoder, probability-domain SPA decoder, log-domain SPA decoder, and simplified log-domain SPA decoder.
Platform: | Size: 8192 | Author: 天天 | Hits:

[Communication-Mobileldpcverilog

Description: verilog编写的ldpc编码的源代码 -ldpc prepared verilog source code
Platform: | Size: 9216 | Author: paul | Hits:

[3G developdecode

Description: LDPC的Verilog程序源代码,包括仿真数据等。文件很大,请慢慢下载-LDPC of Verilog source code, including the simulation data. Large file, please download slowly
Platform: | Size: 10801152 | Author: 陈炜炜 | Hits:

[SCSI-ASPIarchitecure

Description: provide LDPC hardware description language CODE
Platform: | Size: 5087232 | Author: jolin | Hits:

[VHDL-FPGA-Verilogcf_ldpc

Description: ldpc码编码、译码设计,使用vhdl语言编写,包括c语言写的测试代码-ldpc code encoding, decoding design, vhdl language use, including testing c language code
Platform: | Size: 65536 | Author: jinghai | Hits:

[Communicationldpc7_3

Description: the attached file consists of LDPC code (7,3). this code can be easily implemented on fpga kit(sparten-3)
Platform: | Size: 2048 | Author: babi | Hits:

[VHDL-FPGA-VerilogRealization_of_FPGA_for_LDPC_encoding

Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码,它的直接编码运算量较大,通常具有码长的二次方复杂度.为此,利用有效的校验矩阵,来降低编码的复杂度,同时研究利用大规模集成电路实现LDPC码的编码.在ISE 8.2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程,为LDPC码的硬件实现和实际应用提供了依据-Abstract:Low.density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit.For LDPC cod e,the computational overhead for direct encoding operations is large,as the complexity of encod ing is the square of the length of codeword.Hence,this paper reduces the complexity of coding by using effective parity—check matrix,and realizes the encoding device for LDPC code by use of large·scale integrated circuits.The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8.2 software platform ,providing a feasible basis for hardware implementation an d practical application of LDPC code.
Platform: | Size: 165888 | Author: 秦小星 | Hits:

[VHDL-FPGA-Verilogldpc-decoder

Description: LDPC Encoding Code Tetourial VHDL
Platform: | Size: 885760 | Author: moha | Hits:

[VHDL-FPGA-Verilogps_decoder3_12_80_mod

Description: PS-LDPC码译码器的Verilog程序-PS-LDPC code decoder of the Verilog program
Platform: | Size: 29696 | Author: 王昆 | Hits:
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