Search - leon VHDL

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[Other resource] leon2-1.0.30-xst.tar DL : 1: Leon2 CPU VHDL Source Code 欧洲航天局资助开发的LEON CPU,源码遵循GPL -Leon2 CPU VHDL Source Code European Space Agency funded the development of LEON CPU, followed source GPL
Update : 2008-10-13 Size : 1.33mb Publisher : 笑雨
[ARM-PowerPC-ColdFire-MIPS] leon2-1.0.30-xst.tar DL : 0: Leon2 CPU VHDL Source Code 欧洲航天局资助开发的LEON CPU,源码遵循GPL -Leon2 CPU VHDL Source Code European Space Agency funded the development of LEON CPU, followed source GPL
Update : 2025-02-17 Size : 1.33mb Publisher : 笑雨
[VHDL-FPGA-Verilog] Sparc_leon_VHDL DL : 0: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Update : 2025-02-17 Size : 1.79mb Publisher : 韩红
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20 DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Update : 2025-02-17 Size : 671kb Publisher : zhao onely
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Update : 2025-02-17 Size : 735kb Publisher : zhao onely
[VHDL-FPGA-Verilog] cpu-leon3-gr-pci-xc2v3000 DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的PCI位码文件及配置程序。-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of the PCI code files and configuration procedures.
Update : 2025-02-17 Size : 407kb Publisher : zhao onely
[VHDL-FPGA-Verilog] leon3 DL : 0: leon3 source code 虽然gaisler网站上有下载，但是提供此代码，希望能与更多的朋友一起学习leon-leon3 source code although gaisler website to download, but the provision of this code, would like to work with more friends with learning leon
Update : 2025-02-17 Size : 141kb Publisher : CGF
[VHDL-FPGA-Verilog] leon-2.2.tar DL : 0: Update : 2025-02-17 Size : 371kb Publisher : Jackson
[VHDL-FPGA-Verilog] FPU DL : 0: Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
Update : 2025-02-17 Size : 680kb Publisher : Ruchi
[Other] grlib-netlists-1.1.0.tar DL : 0: leon for 3 fpu. The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs.
Update : 2025-02-17 Size : 18.19mb Publisher : serg