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[VHDL-FPGA-Verilogall_packages_20080525.tar

Description: FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We have a tool to read internal delays from an external file (in XML) and add them to the simulation through a SDF file. The most recent version is written in perl and may be downloaded from the "FMF Tools" area. Timing files are provided for over 11,500 part numbers. Also in the tools area is the document type definition (dtd) for the timing files. FMF MAKES NO WARRANTIES ON THE PERFORMANCE OF ANY MODELS IN ITS DATA REPOSITORY. USERS ARE RESPONSIBLE FOR VERIFYING THE ACCURACY OF THE MODELS, SOFTWARE OR TOOLS PROVIDED (TEST SUITES, PACKAGES, TIMING, ETC.).
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