Search - lift verilog

[Graph program] wlift_bior_7_9_JPEG2000

Description: jpeg2000中的空间变换中的DWT，9/7有损小波正变换，这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 9/7 wavelet is detrimental to transform, which is in the ADI blackfin535 DSP platform
Platform: | Size: 44032 | Author: chenlei | Hits:

[Graph program] wlift_inv_bior3_5_JPEG2000

Description: jpeg2000中的空间变换中的DWT，5/3无损小波逆变换，这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 5/3 non-destructive inverse wavelet transform, which is in the ADI blackfin535 DSP platform
Platform: | Size: 41984 | Author: chenlei | Hits:

[Graph program] wlift_inv_bior7_9_JPEG2000

Description: jpeg2000中的空间变换中的DWT，9/7有损小波逆变换，这是在ADI blackfin535 DSP平台下的-JPEG2000 transform space of the DWT, 9/7 inverse wavelet transform detrimental, which is in the ADI blackfin535 DSP platform
Platform: | Size: 43008 | Author: chenlei | Hits:

[Other] 97_2D_2Level

Description: 這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder-This is a two-dimensional lift-style 9/7 discrete wavelet of Verilog source code, this is Encoder
Platform: | Size: 7728128 | Author: chiahao | Hits:

[Other systems] dianti

Description: 基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.
Platform: | Size: 2048 | Author: xiaoyong | Hits:

[VHDL-FPGA-Verilog] diantikongzhiqi

Description: 基于Verilog的八层电梯设计，能够实现自动化的电梯控制。-Verilog based on the eight-lift designed to automate the elevator control.
Platform: | Size: 122880 | Author: xiaohao | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] lift

Description: 简易电梯的设计与实现，包含用Verilog语言的编写，电梯的结构和工作原理-Simple elevator design and implementation, including the preparation with the Verilog language, structure and working principle of the lift
Platform: | Size: 310272 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] wavelet

Description: 基于DB8小波变换的verilog代码设计，支持Avalon总线-Verilog DB8 Wavelet Transform Based on code design, support Avalon bus
Platform: | Size: 7168 | Author: jacky | Hits:

[VHDL-FPGA-Verilog] lift-verilogHDL

Description: 利用verilog语言实现一个简单的电梯控制，可借助最小系统开发板进行试验-control lift by using verilong HDL
Platform: | Size: 1024 | Author: 吴国强 | Hits:

[VHDL-FPGA-Verilog] lift

Description: lift verilog HDL code
Platform: | Size: 2048 | Author: awrhgar | Hits:

[VHDL-FPGA-Verilog] elevator_v2

Description: 用verilog语言描述的模拟单电梯的运行过程。方向优先原则。(1)每层电梯入口处设有上下请求按钮（一楼只有上请求，6楼只有下请求），电梯内设有顾客到达层次的停站请求开关。 (2)电梯入口处设有电梯当前所处楼层指示装置及电梯运行模式(上升或下降)指示装置。 (3)电梯每2秒升(降)一层楼。 (4)电梯到达有停站请求的楼层，经过1秒电梯门打开，开门指示灯亮，开门3秒后，电梯进入关门中状态，提示乘客可以按下延迟关门按键，此时指示灯闪烁，2秒后电梯门关闭，电梯继续进行，直至执行完最后一个请求信号后停留在当前层。 (5)能记忆电梯内外所有请求，并按照电梯运行规则按顺序响应，每个请求信号保留至执行后消除。 (6)电梯运行规则（方向优先电梯调度算法）：当电梯处于上升模式时，只响应比电梯所在位置高的上楼请求信号，由下而上逐个执行，直到最后一个上楼请求执行完毕；如果高层有下楼请求，则直接升到由下楼请求的最高层，然后进入下降模式。当电梯处于下降模式时则与上升模式相反。 (7)电梯初始状态为一楼等待状态。 -Simulation with verilog language to describe the operation of a single lift process. Direction priority principle. (A) each elevator entrance and down a request button (on the first floor only on request, 6th floor only under request), equipped with elevators to reach levels of customer request switch stops. (2) Lift the floor where the entrance to lift the current operating mode indicating device and lift (rising or falling) indicating devices. (3) Lift up every two seconds (lower) floor. (4) There are stops the elevator reaches the floor of the request, after one second the elevator doors opened, door lights, open the door three seconds later, the elevator into the closed state, suggesting that delayed passengers can press the button to close the door, then the indicator flashes, 2 seconds after the elevator doors closed, the elevator continues until the last request signal is executed after the stay in the current layer. (5) can memorize all requests outside the elevator
Platform: | Size: 3192832 | Author: 饶全成 | Hits:

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[Graph program] wlift_bior_7_9_JPEG2000

[Graph program] wlift_inv_bior3_5_JPEG2000

[Graph program] wlift_inv_bior7_9_JPEG2000

[Other] 97_2D_2Level

[Other systems] dianti

[VHDL-FPGA-Verilog] diantikongzhiqi

[Linux-Unix] Linux_bc

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] wavelet

[VHDL-FPGA-Verilog] lift-verilogHDL

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] elevator_v2

[VHDL-FPGA-Verilog] elevator

[VHDL-FPGA-Verilog] lift

[assembly language] lift-code

[VHDL-FPGA-Verilog] Elevator

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