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[SCM] dct_source_code

Description: DCT source code,verilog代码。有兴趣的可以参考下。-DCT source code, verilog code. Interested can refer to the next.
Platform: | Size: 26624 | Author: 小步 | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Platform: | Size: 12288 | Author: 田文军 | Hits:

[VHDL-FPGA-Verilog] lms

Description: verilog 关于LMS均衡器的一些很有用的外文资料 需要的下 免费-verilogverilogverilogverilogverilogverilogverilog
Platform: | Size: 5700608 | Author: 不懂什么 | Hits:

[VHDL-FPGA-Verilog] LMS_filter

Description: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Platform: | Size: 350208 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize

Description: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Platform: | Size: 223232 | Author: 陳柏宇 | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: finite impulse response LMS algorithm verilog code
Platform: | Size: 36864 | Author: zcos123 | Hits:

[VHDL-FPGA-Verilog] ifir_64

Description: verilog hdl, quartus.64阶的简单回声抵消器，采用的是基本的LMS算法，简单改进，可用于初期了解。功能背景是对通信领域中，比如打电话时自己的声音到达对方经对方环境多径反射又传回自己这边，即回声。为将回声消除采用回声抵消装置。-64 steps a simple echo canceller is used in the basic LMS algorithm, a simple improvement, can be used for the initial understanding. Functional background in the field of communication, such as a call to reach the other environmental multipath reflections after each other and return to their side, that echo of their own voice. To echo cancellation echo cancellation device.
Platform: | Size: 40244224 | Author: yy | Hits:

[VHDL-FPGA-Verilog] LMS

Description: 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
Platform: | Size: 2048 | Author: he | Hits:

[VHDL-FPGA-Verilog] pipline_lms_and_rls_verilog

Description: 流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。-The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.
Platform: | Size: 3072 | Author: 杨光西 | Hits:

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